/openbmc/linux/drivers/tty/serial/8250/ |
H A D | 8250_ingenic.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de> 6 * Ingenic SoC UART support 26 int fifosize; member 46 return readl(port->membase + (offset << 2)); in early_in() 51 writel(value, port->membase + (offset << 2)); in early_out() 68 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write() 82 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock() 86 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock() 92 struct uart_port *port = &dev->port; in ingenic_earlycon_setup_tail() [all …]
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H A D | 8250_of.c | 1 // SPDX-License-Identifier: GPL-2.0+ 36 struct device_node *np = ofdev->dev.of_node; in of_platform_serial_setup() 37 struct uart_port *port = &up->port; in of_platform_serial_setup() 43 pm_runtime_enable(&ofdev->dev); in of_platform_serial_setup() 44 pm_runtime_get_sync(&ofdev->dev); in of_platform_serial_setup() 46 if (of_property_read_u32(np, "clock-frequency", &clk)) { in of_platform_serial_setup() 49 info->clk = devm_clk_get(&ofdev->dev, NULL); in of_platform_serial_setup() 50 if (IS_ERR(info->clk)) { in of_platform_serial_setup() 51 ret = PTR_ERR(info->clk); in of_platform_serial_setup() 52 if (ret != -EPROBE_DEFER) in of_platform_serial_setup() [all …]
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H A D | 8250_core.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Universal/legacy driver for 8250/16550-type serial ports 9 * Supports: ISA-compatible 8250/16550 ports 12 * userspace-configurable "phantom" ports 48 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option 49 * is unsafe when used on edge-triggered interrupts. 63 * SERIAL_PORT_DFNS tells us about built-in ports that have no 104 * line has been de-asserted. 117 spin_lock(&i->lock); in serial8250_interrupt() 119 l = i->head; in serial8250_interrupt() [all …]
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H A D | 8250_dw.c | 1 // SPDX-License-Identifier: GPL-2.0+ 10 * raised, the LCR needs to be rewritten and the uart status register read. 34 #define DW_UART_USR 0x1f /* UART Status Register */ 37 #define OCTEON_UART_USR 0x27 /* UART Status Register */ 99 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr() 103 value |= d->msr_mask_on; in dw8250_modify_msr() 104 value &= ~d->msr_mask_off; in dw8250_modify_msr() 122 if (up->fcr & UART_FCR_ENABLE_FIFO) { in dw8250_force_idle() 123 lsr = p->serial_in(p, UART_LSR); in dw8250_force_idle() 128 (void)p->serial_in(p, UART_RX); in dw8250_force_idle() [all …]
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H A D | 8250_pxa.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS 37 serial8250_suspend_port(data->line); in serial_pxa_suspend() 46 serial8250_resume_port(data->line); in serial_pxa_resume() 56 { .compatible = "mrvl,pxa-uart", }, 57 { .compatible = "mrvl,mmp-uart", }, 62 /* Uart divisor latch write */ 82 struct pxa8250_data *data = port->private_data; in serial_pxa_pm() 85 clk_prepare_enable(data->clk); in serial_pxa_pm() 87 clk_disable_unprepare(data->clk); in serial_pxa_pm() [all …]
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H A D | 8250_port.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Base port operations for 8250/16550-type serial ports 55 * Here we define the default xmit fifo size used for each type of UART. 255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement 256 * workaround of errata A-008006 which states that tx_loadsz should 268 .name = "Palmchip BK-3103", 326 .name = "Broadcom BCM7271 UART", 335 /* Uart divisor latch read */ 345 /* Uart divisor latch write */ 354 offset = offset << p->regshift; in hub6_serial_in() [all …]
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H A D | 8250_bcm2835aux.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Serial port driver for BCM2835AUX UART 10 * The bcm2835aux is capable of RTS auto flow-control, but this driver doesn't 37 * struct bcm2835aux_data - driver private data of BCM2835 auxiliary UART 54 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) { in bcm2835aux_rs485_start_tx() 55 struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev); in bcm2835aux_rs485_start_tx() 57 data->cntl &= ~BCM2835_AUX_UART_CNTL_RXEN; in bcm2835aux_rs485_start_tx() 58 serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl); in bcm2835aux_rs485_start_tx() 63 * flags besides RTS. So no need for a read-modify-write. in bcm2835aux_rs485_start_tx() 65 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND) in bcm2835aux_rs485_start_tx() [all …]
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H A D | 8250_uniphier.c | 1 // SPDX-License-Identifier: GPL-2.0+ 17 * - MMIO32 (regshift = 2) 18 * - FCR is not at 2, but 3 19 * - LCR and MCR are not at 3 and 4, they share 4 20 * - No SCR (Instead, CHAR can be used as a scratch register) 21 * - Divisor latch at 9, no divisor latch access bit 43 if (!device->port.membase) in uniphier_early_console_setup() 44 return -ENODEV; in uniphier_early_console_setup() 47 device->port.iotype = UPIO_MEM32; in uniphier_early_console_setup() 48 device->port.regshift = UNIPHIER_UART_REGSHIFT; in uniphier_early_console_setup() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/serial/ |
H A D | samsung_uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org> 14 Each Samsung UART should have an alias correctly numbered in the "aliases" 15 node, according to serialN format, where N is the port number (non-negative 21 - items: 22 - const: samsung,exynosautov9-uart [all …]
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/openbmc/linux/drivers/tty/serial/ |
H A D | sccnxp.c | 1 // SPDX-License-Identifier: GPL-2.0+ 24 #include <linux/platform_data/serial-sccnxp.h> 27 #define SCCNXP_NAME "uart-sccnxp" 93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 106 unsigned int fifosize; member 112 struct uart_driver uart; member 142 .fifosize = 3, 153 .fifosize = 3, 164 .fifosize = 3, [all …]
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H A D | samsung_tty.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics 12 * UERSTAT register in the UART blocks, and keeps marking some of the 21 * BJD, 04-Nov-2004 25 #include <linux/dma-mapping.h> 46 /* UART name and device definitions */ 76 unsigned int fifosize; member 89 /* uart port features */ 97 const unsigned int fifosize[UART_NR]; member 166 #define portaddr(port, reg) ((port)->membase + (reg)) [all …]
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H A D | apbuart.c | 1 // SPDX-License-Identifier: GPL-2.0 10 * Copyright (C) 2008 Gilead Kutnick <kutnickg@zin-tech.com> 71 unsigned int max_chars = port->fifosize; in apbuart_rx_chars() 76 while (UART_RX_DATA(status) && (max_chars--)) { in apbuart_rx_chars() 81 port->icount.rx++; in apbuart_rx_chars() 89 port->icount.brk++; in apbuart_rx_chars() 93 port->icount.parity++; in apbuart_rx_chars() 95 port->icount.frame++; in apbuart_rx_chars() 98 port->icount.overrun++; in apbuart_rx_chars() 100 rsr &= port->read_status_mask; in apbuart_rx_chars() [all …]
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H A D | bcm63xx_uart.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Serial driver for BCM63xx integrated UART. 37 * - rx fifo full 38 * - rx fifo above threshold 39 * - rx fifo not empty for too long 53 * - tx fifo empty 54 * - tx fifo below threshold 71 * handy uart register accessor 76 return __raw_readl(port->membase + offset); in bcm_uart_readl() 82 __raw_writel(value, port->membase + offset); in bcm_uart_writel() [all …]
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H A D | meson_uart.c | 1 // SPDX-License-Identifier: GPL-2.0 102 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty() 111 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx() 113 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx() 120 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx() 122 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx() 130 free_irq(port->irq, port); in meson_uart_shutdown() 132 spin_lock_irqsave(&port->lock, flags); in meson_uart_shutdown() 134 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown() 137 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown() [all …]
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H A D | msm_serial.c | 1 // SPDX-License-Identifier: GPL-2.0 13 #include <linux/dma-mapping.h> 172 struct uart_port uart; member 186 return container_of(up, struct msm_port, uart); in to_msm_port() 192 writel_relaxed(val, port->membase + off); in msm_write() 198 return readl_relaxed(port->membase + off); in msm_read() 210 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo() 222 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4() 233 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs() 236 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs() [all …]
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H A D | pch_uart.c | 1 // SPDX-License-Identifier: GPL-2.0 37 /* Set the max number of UART port 246 * struct pch_uart_driver_data - private data structure for UART-DMA 247 * @port_type: The type of UART port 248 * @line_no: UART port line number (0, 1, 2...) 299 struct eg20t_port *priv = file->private_data; in port_show_regs() 309 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs() 310 "PCH EG20T port[%d] regs:\n", priv->port.line); in port_show_regs() 312 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs() 314 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs() [all …]
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H A D | amba-pl011.c | 1 // SPDX-License-Identifier: GPL-2.0+ 9 * Copyright (C) 2010 ST-Ericsson SA 11 * This is a generic driver for ARM AMBA-type serial ports. They 12 * have a lot of 16550-like features, but are not register compatible. 35 #include <linux/dma-mapping.h> 82 /* The size of the array - must be last */ 262 unsigned int fifosize; /* vendor-specific */ member 263 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 282 return uap->reg_offset[reg]; in pl011_reg_to_offset() 288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_read() [all …]
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H A D | 21285.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Driver for the serial port on the 21285 StrongArm-110 core logic chip. 19 #include <asm/mach-types.h> 42 static const char serial21285_name[] = "Footbridge UART"; 46 * this, use bits of the private_data pointer of the uart port structure. 53 unsigned long *private_data = (unsigned long *)&port->private_data; in is_enabled() 62 unsigned long *private_data = (unsigned long *)&port->private_data; in enable() 69 unsigned long *private_data = (unsigned long *)&port->private_data; in disable() 84 * BAUD_BASE / baud - 1 88 * int(BAUD_BASE / baud - 0.5) -> [all …]
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H A D | amba-pl010.c | 1 // SPDX-License-Identifier: GPL-2.0+ 10 * This is a generic driver for ARM AMBA-type serial ports. They 11 * have a lot of 16550-like features, but are not register compatible. 65 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx() 67 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx() 76 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx() 78 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx() 87 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx() 89 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_rx() 97 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms() [all …]
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H A D | liteuart.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2019-2020 Antmicro <www.antmicro.com> 25 * The definitions below are true for LiteX SoC configured for 8-bit CSR Bus, 26 * 32-bit aligned. 73 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_update_irq_reg() local 76 uart->irq_reg |= mask; in liteuart_update_irq_reg() 78 uart->irq_reg &= ~mask; in liteuart_update_irq_reg() 80 if (port->irq) in liteuart_update_irq_reg() 81 litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); in liteuart_update_irq_reg() 96 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_stop_rx() local [all …]
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H A D | milbeaut_usio.c | 1 // SPDX-License-Identifier: GPL-2.0 15 #define USIO_NAME "mlb-usio-uart" 67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx() 68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx() 69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx() 70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx() 75 struct circ_buf *xmit = &port->state->xmit; in mlb_usio_tx_chars() 78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars() 79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars() 80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars() [all …]
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H A D | ar933x_uart.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Atheros AR933X SoC built-in UART driver 31 #include <asm/mach-ath79/ar933x_uart.h> 35 #define DRIVER_NAME "ar933x-uart" 60 return readl(up->port.membase + offset); in ar933x_uart_read() 66 writel(value, up->port.membase + offset); in ar933x_uart_write() 98 up->ier |= AR933X_UART_INT_TX_EMPTY; in ar933x_uart_start_tx_interrupt() 99 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_start_tx_interrupt() 104 up->ier &= ~AR933X_UART_INT_TX_EMPTY; in ar933x_uart_stop_tx_interrupt() 105 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_stop_tx_interrupt() [all …]
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H A D | sh-sci.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 5 * Copyright (C) 2002 - 2011 Paul Mundt 9 * based off of the old drivers/char/sh-sci.c by: 26 #include <linux/dma-mapping.h> 58 #include "sh-sci.h" 60 /* Offsets into the sci_port->irqs array */ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ [all …]
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/openbmc/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynosautov9.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/clock/samsung,exynosautov9.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/soc/samsung,boot-mode.h> 12 #include <dt-bindings/soc/samsung,exynos-usi.h> 16 #address-cells = <2>; 17 #size-cells = <1>; 19 interrupt-parent = <&gic>; 31 arm-pmu { 32 compatible = "arm,cortex-a76-pmu"; [all …]
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H A D | exynos7885.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/clock/exynos7885.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #address-cells = <2>; 15 #size-cells = <1>; 17 interrupt-parent = <&gic>; 26 arm-a53-pmu { 27 compatible = "arm,cortex-a53-pmu"; 34 interrupt-affinity = <&cpu0>, 42 arm-a73-pmu { [all …]
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