Lines Matching +full:uart +full:- +full:fifosize
1 // SPDX-License-Identifier: GPL-2.0
37 /* Set the max number of UART port
246 * struct pch_uart_driver_data - private data structure for UART-DMA
247 * @port_type: The type of UART port
248 * @line_no: UART port line number (0, 1, 2...)
299 struct eg20t_port *priv = file->private_data; in port_show_regs()
309 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
310 "PCH EG20T port[%d] regs:\n", priv->port.line); in port_show_regs()
312 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
314 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
315 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); in port_show_regs()
316 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
317 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); in port_show_regs()
318 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
319 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); in port_show_regs()
320 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
321 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); in port_show_regs()
322 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
323 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); in port_show_regs()
324 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
325 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); in port_show_regs()
326 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
328 ioread8(priv->membase + PCH_UART_BRCSR)); in port_show_regs()
330 lcr = ioread8(priv->membase + UART_LCR); in port_show_regs()
331 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in port_show_regs()
332 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
333 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); in port_show_regs()
334 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
335 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); in port_show_regs()
336 iowrite8(lcr, priv->membase + UART_LCR); in port_show_regs()
355 .ident = "CM-iTC",
357 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
376 .ident = "COMe-mTT",
378 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
383 .ident = "nanoETXexpress-TT",
385 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
399 /* Return UART clock, checking for board specific clocks. */
409 return (unsigned long)d->driver_data; in pch_uart_get_uartclk()
417 u8 ier = ioread8(priv->membase + UART_IER); in pch_uart_hal_enable_interrupt()
419 iowrite8(ier, priv->membase + UART_IER); in pch_uart_hal_enable_interrupt()
425 u8 ier = ioread8(priv->membase + UART_IER); in pch_uart_hal_disable_interrupt()
427 iowrite8(ier, priv->membase + UART_IER); in pch_uart_hal_disable_interrupt()
437 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); in pch_uart_hal_set_line()
439 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); in pch_uart_hal_set_line()
440 return -EINVAL; in pch_uart_hal_set_line()
447 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); in pch_uart_hal_set_line()
448 return -EINVAL; in pch_uart_hal_set_line()
452 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); in pch_uart_hal_set_line()
453 return -EINVAL; in pch_uart_hal_set_line()
457 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); in pch_uart_hal_set_line()
458 return -EINVAL; in pch_uart_hal_set_line()
465 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n", in pch_uart_hal_set_line()
467 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in pch_uart_hal_set_line()
468 iowrite8(dll, priv->membase + PCH_UART_DLL); in pch_uart_hal_set_line()
469 iowrite8(dlm, priv->membase + PCH_UART_DLM); in pch_uart_hal_set_line()
470 iowrite8(lcr, priv->membase + UART_LCR); in pch_uart_hal_set_line()
479 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", in pch_uart_hal_fifo_reset()
481 return -EINVAL; in pch_uart_hal_fifo_reset()
484 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
485 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, in pch_uart_hal_fifo_reset()
486 priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
487 iowrite8(priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
499 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", in pch_uart_hal_set_fifo()
501 return -EINVAL; in pch_uart_hal_set_fifo()
505 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", in pch_uart_hal_set_fifo()
507 return -EINVAL; in pch_uart_hal_set_fifo()
511 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", in pch_uart_hal_set_fifo()
513 return -EINVAL; in pch_uart_hal_set_fifo()
516 switch (priv->fifo_size) { in pch_uart_hal_set_fifo()
518 priv->trigger_level = in pch_uart_hal_set_fifo()
522 priv->trigger_level = in pch_uart_hal_set_fifo()
526 priv->trigger_level = in pch_uart_hal_set_fifo()
530 priv->trigger_level = in pch_uart_hal_set_fifo()
536 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
538 priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
539 iowrite8(fcr, priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
540 priv->fcr = fcr; in pch_uart_hal_set_fifo()
547 unsigned int msr = ioread8(priv->membase + UART_MSR); in pch_uart_hal_get_modem()
548 priv->dmsr = msr & PCH_UART_MSR_DELTA; in pch_uart_hal_get_modem()
557 struct uart_port *port = &priv->port; in pch_uart_hal_read()
559 lsr = ioread8(priv->membase + UART_LSR); in pch_uart_hal_read()
560 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); in pch_uart_hal_read()
562 lsr = ioread8(priv->membase + UART_LSR)) { in pch_uart_hal_read()
563 rbr = ioread8(priv->membase + PCH_UART_RBR); in pch_uart_hal_read()
566 port->icount.brk++; in pch_uart_hal_read()
580 return ioread8(priv->membase + UART_IIR) &\ in pch_uart_hal_get_iid()
586 return ioread8(priv->membase + UART_LSR); in pch_uart_hal_get_line_status()
593 lcr = ioread8(priv->membase + UART_LCR); in pch_uart_hal_set_break()
599 iowrite8(lcr, priv->membase + UART_LCR); in pch_uart_hal_set_break()
605 struct uart_port *port = &priv->port; in push_rx()
606 struct tty_port *tport = &port->state->port; in push_rx()
617 struct uart_port *port = &priv->port; in dma_push_rx()
618 struct tty_port *tport = &port->state->port; in dma_push_rx()
623 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", in dma_push_rx()
624 size - room); in dma_push_rx()
628 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); in dma_push_rx()
630 port->icount.rx += room; in dma_push_rx()
640 if (priv->chan_tx) { in pch_free_dma()
641 dma_release_channel(priv->chan_tx); in pch_free_dma()
642 priv->chan_tx = NULL; in pch_free_dma()
644 if (priv->chan_rx) { in pch_free_dma()
645 dma_release_channel(priv->chan_rx); in pch_free_dma()
646 priv->chan_rx = NULL; in pch_free_dma()
649 if (priv->rx_buf_dma) { in pch_free_dma()
650 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, in pch_free_dma()
651 priv->rx_buf_dma); in pch_free_dma()
652 priv->rx_buf_virt = NULL; in pch_free_dma()
653 priv->rx_buf_dma = 0; in pch_free_dma()
663 if ((chan->chan_id == param->chan_id) && (param->dma_dev == in filter()
664 chan->device->dev)) { in filter()
665 chan->private = param; in filter()
684 dma_dev = pci_get_slot(priv->pdev->bus, in pch_request_dma()
685 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0)); in pch_request_dma()
688 param = &priv->param_tx; in pch_request_dma()
689 param->dma_dev = &dma_dev->dev; in pch_request_dma()
690 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ in pch_request_dma()
692 param->tx_reg = port->mapbase + UART_TX; in pch_request_dma()
695 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", in pch_request_dma()
700 priv->chan_tx = chan; in pch_request_dma()
703 param = &priv->param_rx; in pch_request_dma()
704 param->dma_dev = &dma_dev->dev; in pch_request_dma()
705 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ in pch_request_dma()
707 param->rx_reg = port->mapbase + UART_RX; in pch_request_dma()
710 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", in pch_request_dma()
712 dma_release_channel(priv->chan_tx); in pch_request_dma()
713 priv->chan_tx = NULL; in pch_request_dma()
719 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, in pch_request_dma()
720 &priv->rx_buf_dma, GFP_KERNEL); in pch_request_dma()
721 priv->chan_rx = chan; in pch_request_dma()
729 struct uart_port *port = &priv->port; in pch_dma_rx_complete()
732 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); in pch_dma_rx_complete()
733 count = dma_push_rx(priv, priv->trigger_level); in pch_dma_rx_complete()
735 tty_flip_buffer_push(&port->state->port); in pch_dma_rx_complete()
736 async_tx_ack(priv->desc_rx); in pch_dma_rx_complete()
744 struct uart_port *port = &priv->port; in pch_dma_tx_complete()
745 struct scatterlist *sg = priv->sg_tx_p; in pch_dma_tx_complete()
748 for (i = 0; i < priv->nent; i++, sg++) in pch_dma_tx_complete()
751 async_tx_ack(priv->desc_tx); in pch_dma_tx_complete()
752 dma_unmap_sg(port->dev, priv->sg_tx_p, priv->orig_nent, DMA_TO_DEVICE); in pch_dma_tx_complete()
753 priv->tx_dma_use = 0; in pch_dma_tx_complete()
754 priv->nent = 0; in pch_dma_tx_complete()
755 priv->orig_nent = 0; in pch_dma_tx_complete()
756 kfree(priv->sg_tx_p); in pch_dma_tx_complete()
765 if (!priv->start_rx) { in handle_rx_to()
770 buf = &priv->rxbuf; in handle_rx_to()
772 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); in handle_rx_to()
773 ret = push_rx(priv, buf->buf, rx_size); in handle_rx_to()
776 } while (rx_size == buf->size); in handle_rx_to()
788 struct uart_port *port = &priv->port; in dma_handle_rx()
793 sg = &priv->sg_rx; in dma_handle_rx()
795 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ in dma_handle_rx()
797 sg_dma_len(sg) = priv->trigger_level; in dma_handle_rx()
799 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), in dma_handle_rx()
800 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt)); in dma_handle_rx()
802 sg_dma_address(sg) = priv->rx_buf_dma; in dma_handle_rx()
804 desc = dmaengine_prep_slave_sg(priv->chan_rx, in dma_handle_rx()
811 priv->desc_rx = desc; in dma_handle_rx()
812 desc->callback = pch_dma_rx_complete; in dma_handle_rx()
813 desc->callback_param = priv; in dma_handle_rx()
814 desc->tx_submit(desc); in dma_handle_rx()
815 dma_async_issue_pending(priv->chan_rx); in dma_handle_rx()
822 struct uart_port *port = &priv->port; in handle_tx()
823 struct circ_buf *xmit = &port->state->xmit; in handle_tx()
827 if (!priv->start_tx) { in handle_tx()
828 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", in handle_tx()
831 priv->tx_empty = 1; in handle_tx()
835 fifo_size = max(priv->fifo_size, 1); in handle_tx()
837 if (port->x_char) { in handle_tx()
838 iowrite8(port->x_char, priv->membase + PCH_UART_THR); in handle_tx()
839 port->icount.tx++; in handle_tx()
840 port->x_char = 0; in handle_tx()
842 fifo_size--; in handle_tx()
846 iowrite8(xmit->buf[xmit->tail], priv->membase + PCH_UART_THR); in handle_tx()
848 fifo_size--; in handle_tx()
852 priv->tx_empty = tx_empty; in handle_tx()
864 struct uart_port *port = &priv->port; in dma_handle_tx()
865 struct circ_buf *xmit = &port->state->xmit; in dma_handle_tx()
876 if (!priv->start_tx) { in dma_handle_tx()
877 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", in dma_handle_tx()
880 priv->tx_empty = 1; in dma_handle_tx()
884 if (priv->tx_dma_use) { in dma_handle_tx()
885 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", in dma_handle_tx()
888 priv->tx_empty = 1; in dma_handle_tx()
892 fifo_size = max(priv->fifo_size, 1); in dma_handle_tx()
894 if (port->x_char) { in dma_handle_tx()
895 iowrite8(port->x_char, priv->membase + PCH_UART_THR); in dma_handle_tx()
896 port->icount.tx++; in dma_handle_tx()
897 port->x_char = 0; in dma_handle_tx()
898 fifo_size--; in dma_handle_tx()
901 bytes = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); in dma_handle_tx()
903 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); in dma_handle_tx()
919 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", in dma_handle_tx()
922 priv->tx_dma_use = 1; in dma_handle_tx()
924 priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC); in dma_handle_tx()
925 if (!priv->sg_tx_p) { in dma_handle_tx()
926 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); in dma_handle_tx()
930 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ in dma_handle_tx()
931 sg = priv->sg_tx_p; in dma_handle_tx()
934 if (i == (num - 1)) in dma_handle_tx()
935 sg_set_page(sg, virt_to_page(xmit->buf), in dma_handle_tx()
938 sg_set_page(sg, virt_to_page(xmit->buf), in dma_handle_tx()
942 sg = priv->sg_tx_p; in dma_handle_tx()
943 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); in dma_handle_tx()
945 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); in dma_handle_tx()
948 priv->orig_nent = num; in dma_handle_tx()
949 priv->nent = nent; in dma_handle_tx()
952 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + in dma_handle_tx()
955 ~(UART_XMIT_SIZE - 1)) + sg->offset; in dma_handle_tx()
956 if (i == (nent - 1)) in dma_handle_tx()
962 desc = dmaengine_prep_slave_sg(priv->chan_tx, in dma_handle_tx()
963 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, in dma_handle_tx()
966 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n", in dma_handle_tx()
970 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); in dma_handle_tx()
971 priv->desc_tx = desc; in dma_handle_tx()
972 desc->callback = pch_dma_tx_complete; in dma_handle_tx()
973 desc->callback_param = priv; in dma_handle_tx()
975 desc->tx_submit(desc); in dma_handle_tx()
977 dma_async_issue_pending(priv->chan_tx); in dma_handle_tx()
984 struct uart_port *port = &priv->port; in pch_uart_err_ir()
985 struct tty_struct *tty = tty_port_tty_get(&port->state->port); in pch_uart_err_ir()
993 port->icount.frame++; in pch_uart_err_ir()
998 port->icount.parity++; in pch_uart_err_ir()
1003 port->icount.overrun++; in pch_uart_err_ir()
1009 dev_err(&priv->pdev->dev, error_msg[i]); in pch_uart_err_ir()
1026 spin_lock_irqsave(&priv->lock, flags); in pch_uart_interrupt()
1044 if (priv->use_dma) { in pch_uart_interrupt()
1063 if (priv->use_dma) in pch_uart_interrupt()
1077 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, in pch_uart_interrupt()
1079 ret = -1; in pch_uart_interrupt()
1086 spin_unlock_irqrestore(&priv->lock, flags); in pch_uart_interrupt()
1097 if (priv->tx_empty) in pch_uart_tx_empty()
1140 if (priv->mcr & UART_MCR_AFE) in pch_uart_set_mctrl()
1144 iowrite8(mcr, priv->membase + UART_MCR); in pch_uart_set_mctrl()
1151 priv->start_tx = 0; in pch_uart_stop_tx()
1152 priv->tx_dma_use = 0; in pch_uart_stop_tx()
1161 if (priv->use_dma) { in pch_uart_start_tx()
1162 if (priv->tx_dma_use) { in pch_uart_start_tx()
1163 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", in pch_uart_start_tx()
1169 priv->start_tx = 1; in pch_uart_start_tx()
1177 priv->start_rx = 0; in pch_uart_stop_rx()
1197 spin_lock_irqsave(&priv->lock, flags); in pch_uart_break_ctl()
1199 spin_unlock_irqrestore(&priv->lock, flags); in pch_uart_break_ctl()
1211 priv->tx_empty = 1; in pch_uart_startup()
1213 if (port->uartclk) in pch_uart_startup()
1214 priv->uartclk = port->uartclk; in pch_uart_startup()
1216 port->uartclk = priv->uartclk; in pch_uart_startup()
1225 switch (priv->fifo_size) { in pch_uart_startup()
1241 switch (priv->trigger) { in pch_uart_startup()
1246 trigger_level = priv->fifo_size / 4; in pch_uart_startup()
1249 trigger_level = priv->fifo_size / 2; in pch_uart_startup()
1253 trigger_level = priv->fifo_size - (priv->fifo_size / 8); in pch_uart_startup()
1257 priv->trigger_level = trigger_level; in pch_uart_startup()
1259 fifo_size, priv->trigger); in pch_uart_startup()
1263 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, in pch_uart_startup()
1264 priv->irq_name, priv); in pch_uart_startup()
1268 if (priv->use_dma) in pch_uart_startup()
1271 priv->start_rx = 1; in pch_uart_startup()
1290 dev_err(priv->port.dev, in pch_uart_shutdown()
1295 free_irq(priv->port.irq, priv); in pch_uart_shutdown()
1311 switch (termios->c_cflag & CSIZE) { in pch_uart_set_termios()
1325 if (termios->c_cflag & CSTOPB) in pch_uart_set_termios()
1330 if (termios->c_cflag & PARENB) { in pch_uart_set_termios()
1331 if (termios->c_cflag & PARODD) in pch_uart_set_termios()
1340 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) in pch_uart_set_termios()
1341 priv->mcr |= UART_MCR_AFE; in pch_uart_set_termios()
1343 priv->mcr &= ~UART_MCR_AFE; in pch_uart_set_termios()
1345 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ in pch_uart_set_termios()
1347 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); in pch_uart_set_termios()
1349 spin_lock_irqsave(&priv->lock, flags); in pch_uart_set_termios()
1350 spin_lock(&port->lock); in pch_uart_set_termios()
1352 uart_update_timeout(port, termios->c_cflag, baud); in pch_uart_set_termios()
1357 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); in pch_uart_set_termios()
1363 spin_unlock(&port->lock); in pch_uart_set_termios()
1364 spin_unlock_irqrestore(&priv->lock, flags); in pch_uart_set_termios()
1377 pci_iounmap(priv->pdev, priv->membase); in pch_uart_release_port()
1378 pci_release_regions(priv->pdev); in pch_uart_release_port()
1388 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); in pch_uart_request_port()
1390 return -EBUSY; in pch_uart_request_port()
1392 membase = pci_iomap(priv->pdev, 1, 0); in pch_uart_request_port()
1394 pci_release_regions(priv->pdev); in pch_uart_request_port()
1395 return -EBUSY; in pch_uart_request_port()
1397 priv->membase = port->membase = membase; in pch_uart_request_port()
1408 port->type = priv->port_type; in pch_uart_config_port()
1419 if (serinfo->flags & UPF_LOW_LATENCY) { in pch_uart_verify_port()
1420 dev_info(priv->port.dev, in pch_uart_verify_port()
1421 "PCH UART : Use PIO Mode (without DMA)\n"); in pch_uart_verify_port()
1422 priv->use_dma = 0; in pch_uart_verify_port()
1423 serinfo->flags &= ~UPF_LOW_LATENCY; in pch_uart_verify_port()
1426 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", in pch_uart_verify_port()
1428 return -EOPNOTSUPP; in pch_uart_verify_port()
1430 if (!priv->use_dma) { in pch_uart_verify_port()
1432 if (priv->chan_rx) in pch_uart_verify_port()
1433 priv->use_dma = 1; in pch_uart_verify_port()
1435 dev_info(priv->port.dev, "PCH UART: %s\n", in pch_uart_verify_port()
1436 priv->use_dma ? in pch_uart_verify_port()
1453 status = ioread8(up->membase + UART_LSR); in wait_for_xmitr()
1457 if (--tmout == 0) in wait_for_xmitr()
1463 if (up->port.flags & UPF_CONS_FLOW) { in wait_for_xmitr()
1465 for (tmout = 1000000; tmout; tmout--) { in wait_for_xmitr()
1466 unsigned int msr = ioread8(up->membase + UART_MSR); in wait_for_xmitr()
1478 * Console polling routines for communicate via uart while
1485 u8 lsr = ioread8(priv->membase + UART_LSR); in pch_uart_get_poll_char()
1490 return ioread8(priv->membase + PCH_UART_RBR); in pch_uart_get_poll_char()
1504 ier = ioread8(priv->membase + UART_IER); in pch_uart_put_poll_char()
1511 iowrite8(c, priv->membase + PCH_UART_THR); in pch_uart_put_poll_char()
1518 iowrite8(ier, priv->membase + UART_IER); in pch_uart_put_poll_char()
1554 iowrite8(ch, priv->membase + PCH_UART_THR); in pch_console_putchar()
1572 priv = pch_uart_ports[co->index]; in pch_console_write()
1577 if (priv->port.sysrq) { in pch_console_write()
1583 priv_locked = spin_trylock(&priv->lock); in pch_console_write()
1584 port_locked = spin_trylock(&priv->port.lock); in pch_console_write()
1586 spin_lock(&priv->lock); in pch_console_write()
1587 spin_lock(&priv->port.lock); in pch_console_write()
1593 ier = ioread8(priv->membase + UART_IER); in pch_console_write()
1597 uart_console_write(&priv->port, s, count, pch_console_putchar); in pch_console_write()
1604 iowrite8(ier, priv->membase + UART_IER); in pch_console_write()
1607 spin_unlock(&priv->port.lock); in pch_console_write()
1609 spin_unlock(&priv->lock); in pch_console_write()
1622 * Check whether an invalid uart number has been specified, and in pch_console_setup()
1626 if (co->index >= PCH_UART_NR) in pch_console_setup()
1627 co->index = 0; in pch_console_setup()
1628 port = &pch_uart_ports[co->index]->port; in pch_console_setup()
1630 if (!port || (!port->iobase && !port->membase)) in pch_console_setup()
1631 return -ENODEV; in pch_console_setup()
1633 port->uartclk = pch_uart_get_uartclk(); in pch_console_setup()
1649 .index = -1,
1676 int fifosize; in pch_uart_init_port() local
1681 board = &drv_dat[id->driver_data]; in pch_uart_init_port()
1682 port_type = board->port_type; in pch_uart_init_port()
1694 fifosize = 256; /* EG20T/ML7213: UART0 */ in pch_uart_init_port()
1697 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ in pch_uart_init_port()
1700 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); in pch_uart_init_port()
1707 spin_lock_init(&priv->lock); in pch_uart_init_port()
1711 priv->mapbase = mapbase; in pch_uart_init_port()
1712 priv->iobase = iobase; in pch_uart_init_port()
1713 priv->pdev = pdev; in pch_uart_init_port()
1714 priv->tx_empty = 1; in pch_uart_init_port()
1715 priv->rxbuf.buf = rxbuf; in pch_uart_init_port()
1716 priv->rxbuf.size = PAGE_SIZE; in pch_uart_init_port()
1718 priv->fifo_size = fifosize; in pch_uart_init_port()
1719 priv->uartclk = pch_uart_get_uartclk(); in pch_uart_init_port()
1720 priv->port_type = port_type; in pch_uart_init_port()
1721 priv->port.dev = &pdev->dev; in pch_uart_init_port()
1722 priv->port.iobase = iobase; in pch_uart_init_port()
1723 priv->port.membase = NULL; in pch_uart_init_port()
1724 priv->port.mapbase = mapbase; in pch_uart_init_port()
1725 priv->port.irq = pdev->irq; in pch_uart_init_port()
1726 priv->port.iotype = UPIO_PORT; in pch_uart_init_port()
1727 priv->port.ops = &pch_uart_ops; in pch_uart_init_port()
1728 priv->port.flags = UPF_BOOT_AUTOCONF; in pch_uart_init_port()
1729 priv->port.fifosize = fifosize; in pch_uart_init_port()
1730 priv->port.line = board->line_no; in pch_uart_init_port()
1731 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE); in pch_uart_init_port()
1732 priv->trigger = PCH_UART_HAL_TRIGGER_M; in pch_uart_init_port()
1734 snprintf(priv->irq_name, IRQ_NAME_SIZE, in pch_uart_init_port()
1736 priv->port.line); in pch_uart_init_port()
1738 spin_lock_init(&priv->port.lock); in pch_uart_init_port()
1741 priv->trigger_level = 1; in pch_uart_init_port()
1742 priv->fcr = 0; in pch_uart_init_port()
1744 if (pdev->dev.of_node) in pch_uart_init_port()
1745 of_property_read_u32(pdev->dev.of_node, "clock-frequency" in pch_uart_init_port()
1749 pch_uart_ports[board->line_no] = priv; in pch_uart_init_port()
1751 ret = uart_add_one_port(&pch_uart_driver, &priv->port); in pch_uart_init_port()
1755 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); in pch_uart_init_port()
1763 pch_uart_ports[board->line_no] = NULL; in pch_uart_init_port()
1777 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); in pch_uart_exit_port()
1779 uart_remove_one_port(&pch_uart_driver, &priv->port); in pch_uart_exit_port()
1780 free_page((unsigned long)priv->rxbuf.buf); in pch_uart_exit_port()
1790 pch_uart_ports[priv->port.line] = NULL; in pch_uart_pci_remove()
1802 uart_suspend_port(&pch_uart_driver, &priv->port); in pch_uart_pci_suspend()
1811 uart_resume_port(&pch_uart_driver, &priv->port); in pch_uart_pci_resume()
1854 ret = -EBUSY; in pch_uart_pci_probe()
1884 /* register as UART driver */ in pch_uart_module_init()
1906 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1914 "Override UART default or board specific UART clock");