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/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dsamsung,exynos-thermal.yaml7 title: Samsung Exynos SoC Thermal Management Unit (TMU)
13 For multi-instance tmu each instance should have an alias correctly numbered
19 - samsung,exynos3250-tmu
20 - samsung,exynos4412-tmu
21 - samsung,exynos4210-tmu
22 - samsung,exynos5250-tmu
23 - samsung,exynos5260-tmu
24 # For TMU channel 0, 1 on Exynos5420:
25 - samsung,exynos5420-tmu
26 # For TMU channels 2, 3 and 4 of Exynos5420:
[all …]
H A Dqoriq-thermal.yaml7 title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
15 The version of the device is determined by the TMU IP Block Revision
22 - fsl,qoriq-tmu
23 - fsl,imx8mq-tmu
31 fsl,tmu-range:
38 fsl,tmu-calibration:
54 boolean, if present, the TMU registers are little endian. If absent,
68 - fsl,tmu-range
69 - fsl,tmu-calibration
76 tmu@f0000 {
[all …]
H A Dimx8mm-thermal.yaml13 i.MX8MM has TMU IP to allow temperature measurement, there are
23 - fsl,imx8mm-tmu
24 - fsl,imx8mp-tmu
26 - const: fsl,imx8mn-tmu
27 - const: fsl,imx8mm-tmu
63 compatible = "fsl,imx8mm-tmu";
/openbmc/linux/drivers/clocksource/
H A Dsh_tmu.c3 * SuperH Timer Support - TMU
39 struct sh_tmu_device *tmu; member
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
111 switch (ch->tmu->model) { in sh_tmu_write()
113 return iowrite8(value, ch->tmu->mapbase + 2); in sh_tmu_write()
115 return iowrite8(value, ch->tmu->mapbase + 4); in sh_tmu_write()
132 raw_spin_lock_irqsave(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
141 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
[all …]
/openbmc/linux/drivers/thermal/
H A Dimx8mm_thermal.c21 #define TER 0x0 /* TMU enable */
23 #define TRITSR 0x20 /* TMU immediate temp */
24 /* TMU calibration data registers */
52 /* TMU OCOTP calibration data bitfields */
100 struct imx8mm_tmu *tmu = sensor->priv; in imx8mm_tmu_get_temp() local
103 val = readl_relaxed(tmu->base + TRITSR) & TRITSR_TEMP0_VAL_MASK; in imx8mm_tmu_get_temp()
107 * ERR051272: TMU: Bit 31 of registers TMU_TSCR/TMU_TRITSR/TMU_TRATSR invalid in imx8mm_tmu_get_temp()
120 struct imx8mm_tmu *tmu = sensor->priv; in imx8mp_tmu_get_temp() local
124 val = readl_relaxed(tmu->base + TRITSR); in imx8mp_tmu_get_temp()
144 struct imx8mm_tmu *tmu = sensor->priv; in tmu_get_temp() local
[all …]
H A Dqoriq_thermal.c54 #define REGS_V2_TMSAR(n) (0x304 + 16 * (n)) /* TMU monitoring
96 * For TMU Rev1: in tmu_get_temp()
104 * For TMU Rev2: in tmu_get_temp()
192 len = of_property_count_u32_elems(np, "fsl,tmu-range"); in qoriq_tmu_calibration()
199 val = of_property_read_u32_array(np, "fsl,tmu-range", data->ttrcr, len); in qoriq_tmu_calibration()
209 calibration = of_get_property(np, "fsl,tmu-calibration", &len); in qoriq_tmu_calibration()
333 qoriq_tmu_init_device(data); /* TMU initialization */ in qoriq_tmu_probe()
335 ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */ in qoriq_tmu_probe()
381 { .compatible = "fsl,qoriq-tmu", },
382 { .compatible = "fsl,imx8mq-tmu", },
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,tmu.yaml4 $id: http://devicetree.org/schemas/timer/renesas,tmu.yaml#
7 title: Renesas R-Mobile/R-Car Timer Unit (TMU)
14 The TMU is a 32-bit timer/counter with configurable clock inputs and
18 are independent. The TMU hardware supports up to three channels.
24 - renesas,tmu-r8a7740 # R-Mobile A1
25 - renesas,tmu-r8a774a1 # RZ/G2M
26 - renesas,tmu-r8a774b1 # RZ/G2N
27 - renesas,tmu-r8a774c0 # RZ/G2E
28 - renesas,tmu-r8a774e1 # RZ/G2H
29 - renesas,tmu-r8a7778 # R-Car M1A
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/openbmc/linux/drivers/thunderbolt/
H A Dtmu.c3 * Thunderbolt Time Management Unit (TMU) support
73 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_set_tmu_mode_params()
81 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_set_tmu_mode_params()
86 sw->tmu.cap + TMU_RTR_CS_15, 1); in tb_switch_set_tmu_mode_params()
100 sw->tmu.cap + TMU_RTR_CS_15, 1); in tb_switch_set_tmu_mode_params()
108 sw->tmu.cap + TMU_RTR_CS_18, 1); in tb_switch_set_tmu_mode_params()
116 sw->tmu.cap + TMU_RTR_CS_18, 1); in tb_switch_set_tmu_mode_params()
128 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_tmu_ucap_is_supported()
141 sw->tmu.cap + TMU_RTR_CS_3, 1); in tb_switch_tmu_rate_read()
155 sw->tmu.cap + TMU_RTR_CS_3, 1); in tb_switch_tmu_rate_write()
[all …]
H A Dtb.h78 * enum tb_switch_tmu_mode - TMU mode
79 * @TB_SWITCH_TMU_MODE_OFF: TMU is off
85 * Ordering is based on TMU accuracy level (highest last).
96 * struct tb_switch_tmu - Structure holding router TMU configuration
97 * @cap: Offset to the TMU capability (%0 if not found)
99 * @mode: TMU mode related to the upstream router. Reflects the HW
101 * @mode_request: TMU mode requested to set. Related to upstream router.
120 * @tmu: The switch TMU configuration
133 * @cap_vsec_tmu: Offset to the TMU vendor specific capability (%0 if not found)
173 struct tb_switch_tmu tmu; member
[all …]
/openbmc/linux/Documentation/driver-api/thermal/
H A Dexynos_thermal.rst14 TMU controller Description:
46 TMU(Thermal Management Unit) in Exynos4/5 generates interrupt
64 TMU driver description:
74 TMU configuration data -----> TMU Driver <----> Exynos Core thermal wrapper
78 a) TMU configuration data:
79 This consist of TMU register offsets/bitfields
82 are used to configure the TMU.
83 b) TMU driver:
84 This component initialises the TMU controller and sets different
H A Dexynos_thermal_emulation.rst14 TMU's operation. User can set temperature manually with software code
15 and TMU will read current temperature from user value not from sensor's
/openbmc/u-boot/drivers/power/
H A Dexynos-tmu.c23 #include <tmu.h>
24 #include <asm/arch/tmu.h>
78 /* TMU device specific details and status */
80 /* base Address for the TMU */
82 /* mux Address for the TMU */
92 /* enum value indicating status of the TMU */
104 * @return current temperature of the chip as sensed by TMU
134 * Monitors status of the TMU device and exynos temperature
175 * Get TMU specific pre-defined values from FDT
188 /* Get the node from FDT for TMU */ in get_tmu_fdt_values()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/exynos/
H A Dtmu.txt5 - compatible : Should be "samsung,exynos-tmu" for TMU
10 - samsung,start-warning : Temperature at which TMU starts giving warning (degree celsius)
11 - samsung,start-tripping : Temperature at which TMU shuts down the system (degree celsius)
13 in case TMU fails to power off (degree celsius)
32 tmu@10060000 {
33 compatible = "samsung,exynos-tmu"
/openbmc/linux/drivers/platform/x86/intel/
H A Dbxtwc_tmu.c3 * Intel BXT Whiskey Cove PMIC TMU driver
7 * This driver adds TMU (Time Management Unit) support for Intel BXT platform.
8 * It enables the alarm wake-up functionality in the TMU unit of Whiskey Cove
38 /* Read TMU interrupt reg */ in bxt_wcove_tmu_irq_handler()
41 /* clear TMU irq */ in bxt_wcove_tmu_irq_handler()
74 /* Unmask TMU second level Wake & System alarm */ in bxt_wcove_tmu_probe()
87 /* Mask TMU interrupts */ in bxt_wcove_tmu_remove()
136 MODULE_DESCRIPTION("BXT Whiskey Cove TMU Driver");
/openbmc/u-boot/drivers/net/pfe_eth/
H A Dpfe_cmd.c159 * This function is used to read the drop statistics from the TMU
165 * @param tmu TMU number (0 - 3)
171 u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset) in qm_read_drop_stat() argument
176 writel((tmu << 8) | queue, TMU_TEQ_CTRL); in qm_read_drop_stat()
177 writel((tmu << 8) | queue, TMU_LLM_CTRL); in qm_read_drop_stat()
179 qtotal[tmu][queue] += val; in qm_read_drop_stat()
181 *total_drops = qtotal[tmu][queue]; in qm_read_drop_stat()
183 qtotal[tmu][queue] = 0; in qm_read_drop_stat()
187 static ssize_t tmu_queue_stats(char *buf, int tmu, int queue) in tmu_queue_stats() argument
192 printf("%d-%02d, ", tmu, queue); in tmu_queue_stats()
[all …]
/openbmc/linux/drivers/thermal/samsung/
H A Dexynos_tmu.c3 * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit)
139 * struct exynos_tmu_data : A structure to hold the private data of the TMU
141 * @id: identifier of the one instance of the TMU controller.
142 * @base: base address of the single instance of the TMU controller.
143 * @base_second: base address of the common registers of the TMU controller.
144 * @irq: irq number of the TMU controller.
150 * @sclk: pointer to the clock structure for accessing the tmu special clk.
162 * @regulator: pointer to the TMU regulator structure.
166 * @enabled: current status of TMU device
169 * @tmu_initialize: SoC specific TMU initialization method
[all …]
H A DKconfig7 If you say yes here you get support for the TMU (Thermal Management
9 the TMU, reports temperature and handles cooling action if defined.
10 This driver uses the Exynos core thermal APIs and TMU configuration
/openbmc/linux/drivers/gpu/drm/vc4/
H A Dvc4_validate_shaders.c31 * (reading it as a texture, uniform data, or direct-addressed TMU
157 int tmu) in record_texture_sample() argument
170 &validation_state->tmu_setup[tmu], in record_texture_sample()
177 validation_state->tmu_setup[tmu].p_offset[i] = ~0; in record_texture_sample()
193 int tmu = waddr > QPU_W_TMU0_B; in check_tmu_write() local
195 bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0; in check_tmu_write()
203 DRM_DEBUG("direct TMU read used small immediate\n"); in check_tmu_write()
212 DRM_DEBUG("direct TMU load wasn't an add\n"); in check_tmu_write()
223 DRM_DEBUG("direct TMU load wasn't clamped\n"); in check_tmu_write()
229 DRM_DEBUG("direct TMU load wasn't clamped\n"); in check_tmu_write()
[all …]
/openbmc/linux/arch/sh/kernel/cpu/
H A Dclock-cpg.c60 clk_add_alias("fck", "sh-tmu-sh3.0", "peripheral_clk", NULL); in cpg_clk_init()
61 clk_add_alias("fck", "sh-tmu.0", "peripheral_clk", NULL); in cpg_clk_init()
62 clk_add_alias("fck", "sh-tmu.1", "peripheral_clk", NULL); in cpg_clk_init()
63 clk_add_alias("fck", "sh-tmu.2", "peripheral_clk", NULL); in cpg_clk_init()
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410.dtsi90 tmu_cpu0: tmu@10060000 {
91 compatible = "samsung,exynos5420-tmu";
99 tmu_cpu1: tmu@10064000 {
100 compatible = "samsung,exynos5420-tmu";
108 tmu_cpu2: tmu@10068000 {
109 compatible = "samsung,exynos5420-tmu";
117 tmu_cpu3: tmu@1006c000 {
118 compatible = "samsung,exynos5420-tmu";
/openbmc/u-boot/include/
H A Dtmu.h31 * Monitors status of the TMU device and exynos temperature
40 * Initialize TMU device
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-imx8mq.dtsi146 tmu: tmu@30260000 { label
147 compatible = "fsl,imx8mq-tmu";
152 fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
153 fsl,tmu-calibration = <0x00000000 0x00000020
204 thermal-sensors = <&tmu>;
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7786.c155 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
156 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]),
157 CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP010]),
158 CLKDEV_ICK_ID("fck", "sh-tmu.3", &mstp_clks[MSTP011]),
/openbmc/u-boot/board/samsung/common/
H A Dboard.c12 #include <tmu.h>
68 * sensing and TMU status was changed back from NORMAL to INIT. in boot_temp_check()
73 debug("EXYNOS_TMU: Unknown TMU state\n"); in boot_temp_check()
83 debug("%s: Failed to init TMU\n", __func__); in board_init()
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1046a.dtsi128 thermal-sensors = <&tmu 0>;
148 thermal-sensors = <&tmu 1>;
168 thermal-sensors = <&tmu 2>;
188 thermal-sensors = <&tmu 3>;
219 thermal-sensors = <&tmu 4>;
441 tmu: tmu@1f00000 { label
442 compatible = "fsl,qoriq-tmu";
445 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
446 fsl,tmu-calibration =

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