12dfef650SFabio Estevam // SPDX-License-Identifier: GPL-2.0
22dfef650SFabio Estevam //
32dfef650SFabio Estevam // Copyright 2016 Freescale Semiconductor, Inc.
443528445SJia Hongtao
551904045SAnson Huang #include <linux/clk.h>
643528445SJia Hongtao #include <linux/err.h>
743528445SJia Hongtao #include <linux/io.h>
8ce68eecaSAnson Huang #include <linux/module.h>
943528445SJia Hongtao #include <linux/of.h>
10ce68eecaSAnson Huang #include <linux/platform_device.h>
114316237bSAndrey Smirnov #include <linux/regmap.h>
124316237bSAndrey Smirnov #include <linux/sizes.h>
1343528445SJia Hongtao #include <linux/thermal.h>
1447fa116eSYuantian Tang #include <linux/units.h>
1543528445SJia Hongtao
16fd843309SAndrey Smirnov #include "thermal_hwmon.h"
1743528445SJia Hongtao
1843528445SJia Hongtao #define SITES_MAX 16
199809797bSYuantian Tang #define TMR_DISABLE 0x0
209809797bSYuantian Tang #define TMR_ME 0x80000000
219809797bSYuantian Tang #define TMR_ALPF 0x0c000000
229809797bSYuantian Tang #define TMR_ALPF_V2 0x03000000
239809797bSYuantian Tang #define TMTMIR_DEFAULT 0x0000000f
249809797bSYuantian Tang #define TIER_DISABLE 0x0
259809797bSYuantian Tang #define TEUMR0_V2 0x51009c00
2647fa116eSYuantian Tang #define TMSARA_V2 0xe
279809797bSYuantian Tang #define TMU_VER1 0x1
289809797bSYuantian Tang #define TMU_VER2 0x2
2943528445SJia Hongtao
304316237bSAndrey Smirnov #define REGS_TMR 0x000 /* Mode Register */
314316237bSAndrey Smirnov #define TMR_DISABLE 0x0
324316237bSAndrey Smirnov #define TMR_ME 0x80000000
334316237bSAndrey Smirnov #define TMR_ALPF 0x0c000000
344316237bSAndrey Smirnov
354316237bSAndrey Smirnov #define REGS_TMTMIR 0x008 /* Temperature measurement interval Register */
364316237bSAndrey Smirnov #define TMTMIR_DEFAULT 0x0000000f
374316237bSAndrey Smirnov
384316237bSAndrey Smirnov #define REGS_V2_TMSR 0x008 /* monitor site register */
394316237bSAndrey Smirnov
404316237bSAndrey Smirnov #define REGS_V2_TMTMIR 0x00c /* Temperature measurement interval Register */
414316237bSAndrey Smirnov
424316237bSAndrey Smirnov #define REGS_TIER 0x020 /* Interrupt Enable Register */
434316237bSAndrey Smirnov #define TIER_DISABLE 0x0
444316237bSAndrey Smirnov
454316237bSAndrey Smirnov
464316237bSAndrey Smirnov #define REGS_TTCFGR 0x080 /* Temperature Configuration Register */
474316237bSAndrey Smirnov #define REGS_TSCFGR 0x084 /* Sensor Configuration Register */
484316237bSAndrey Smirnov
494316237bSAndrey Smirnov #define REGS_TRITSR(n) (0x100 + 16 * (n)) /* Immediate Temperature
504316237bSAndrey Smirnov * Site Register
5143528445SJia Hongtao */
5236564d7eSAndrey Smirnov #define TRITSR_V BIT(31)
53f12d60c8SPeng Fan #define TRITSR_TP5 BIT(9)
5447fa116eSYuantian Tang #define REGS_V2_TMSAR(n) (0x304 + 16 * (n)) /* TMU monitoring
5547fa116eSYuantian Tang * site adjustment register
5647fa116eSYuantian Tang */
574316237bSAndrey Smirnov #define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n
584316237bSAndrey Smirnov * Control Register
594316237bSAndrey Smirnov */
60*2584d6bbSPeng Fan #define NUM_TTRCR_V1 4
61*2584d6bbSPeng Fan #define NUM_TTRCR_MAX 16
62*2584d6bbSPeng Fan
634316237bSAndrey Smirnov #define REGS_IPBRR(n) (0xbf8 + 4 * (n)) /* IP Block Revision
644316237bSAndrey Smirnov * Register n
654316237bSAndrey Smirnov */
664316237bSAndrey Smirnov #define REGS_V2_TEUMR(n) (0xf00 + 4 * (n))
6743528445SJia Hongtao
6843528445SJia Hongtao /*
6943528445SJia Hongtao * Thermal zone data
7043528445SJia Hongtao */
717797ff42SYuantian Tang struct qoriq_sensor {
727797ff42SYuantian Tang int id;
737797ff42SYuantian Tang };
747797ff42SYuantian Tang
7543528445SJia Hongtao struct qoriq_tmu_data {
769809797bSYuantian Tang int ver;
77*2584d6bbSPeng Fan u32 ttrcr[NUM_TTRCR_MAX];
784316237bSAndrey Smirnov struct regmap *regmap;
7951904045SAnson Huang struct clk *clk;
80b319da1bSAndrey Smirnov struct qoriq_sensor sensor[SITES_MAX];
8143528445SJia Hongtao };
8243528445SJia Hongtao
qoriq_sensor_to_data(struct qoriq_sensor * s)83b319da1bSAndrey Smirnov static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s)
84b319da1bSAndrey Smirnov {
85b319da1bSAndrey Smirnov return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
86b319da1bSAndrey Smirnov }
87b319da1bSAndrey Smirnov
tmu_get_temp(struct thermal_zone_device * tz,int * temp)883e7494b4SDaniel Lezcano static int tmu_get_temp(struct thermal_zone_device *tz, int *temp)
8943528445SJia Hongtao {
905f68d078SDaniel Lezcano struct qoriq_sensor *qsensor = thermal_zone_device_priv(tz);
91b319da1bSAndrey Smirnov struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
9243528445SJia Hongtao u32 val;
9336564d7eSAndrey Smirnov /*
9436564d7eSAndrey Smirnov * REGS_TRITSR(id) has the following layout:
9536564d7eSAndrey Smirnov *
9647fa116eSYuantian Tang * For TMU Rev1:
9736564d7eSAndrey Smirnov * 31 ... 7 6 5 4 3 2 1 0
9836564d7eSAndrey Smirnov * V TEMP
9936564d7eSAndrey Smirnov *
10036564d7eSAndrey Smirnov * Where V bit signifies if the measurement is ready and is
10136564d7eSAndrey Smirnov * within sensor range. TEMP is an 8 bit value representing
10247fa116eSYuantian Tang * temperature in Celsius.
10347fa116eSYuantian Tang
10447fa116eSYuantian Tang * For TMU Rev2:
10547fa116eSYuantian Tang * 31 ... 8 7 6 5 4 3 2 1 0
10647fa116eSYuantian Tang * V TEMP
10747fa116eSYuantian Tang *
10847fa116eSYuantian Tang * Where V bit signifies if the measurement is ready and is
10947fa116eSYuantian Tang * within sensor range. TEMP is an 9 bit value representing
11047fa116eSYuantian Tang * temperature in KelVin.
11136564d7eSAndrey Smirnov */
1129301575dSPeng Fan
1139301575dSPeng Fan regmap_read(qdata->regmap, REGS_TMR, &val);
1149301575dSPeng Fan if (!(val & TMR_ME))
1159301575dSPeng Fan return -EAGAIN;
1169301575dSPeng Fan
11736564d7eSAndrey Smirnov if (regmap_read_poll_timeout(qdata->regmap,
11836564d7eSAndrey Smirnov REGS_TRITSR(qsensor->id),
11936564d7eSAndrey Smirnov val,
12036564d7eSAndrey Smirnov val & TRITSR_V,
12136564d7eSAndrey Smirnov USEC_PER_MSEC,
12236564d7eSAndrey Smirnov 10 * USEC_PER_MSEC))
12336564d7eSAndrey Smirnov return -ENODATA;
12443528445SJia Hongtao
125f12d60c8SPeng Fan if (qdata->ver == TMU_VER1) {
12647fa116eSYuantian Tang *temp = (val & GENMASK(7, 0)) * MILLIDEGREE_PER_DEGREE;
127f12d60c8SPeng Fan } else {
128f12d60c8SPeng Fan if (val & TRITSR_TP5)
129f12d60c8SPeng Fan *temp = milli_kelvin_to_millicelsius((val & GENMASK(8, 0)) *
130f12d60c8SPeng Fan MILLIDEGREE_PER_DEGREE + 500);
13147fa116eSYuantian Tang else
13247fa116eSYuantian Tang *temp = kelvin_to_millicelsius(val & GENMASK(8, 0));
133f12d60c8SPeng Fan }
13443528445SJia Hongtao
13543528445SJia Hongtao return 0;
13643528445SJia Hongtao }
13743528445SJia Hongtao
1383e7494b4SDaniel Lezcano static const struct thermal_zone_device_ops tmu_tz_ops = {
1397797ff42SYuantian Tang .get_temp = tmu_get_temp,
1407797ff42SYuantian Tang };
1417797ff42SYuantian Tang
qoriq_tmu_register_tmu_zone(struct device * dev,struct qoriq_tmu_data * qdata)14203036625SAndrey Smirnov static int qoriq_tmu_register_tmu_zone(struct device *dev,
14303036625SAndrey Smirnov struct qoriq_tmu_data *qdata)
14443528445SJia Hongtao {
1459301575dSPeng Fan int id, sites = 0;
14643528445SJia Hongtao
1477797ff42SYuantian Tang for (id = 0; id < SITES_MAX; id++) {
14811ef00f7SAndrey Smirnov struct thermal_zone_device *tzd;
149b319da1bSAndrey Smirnov struct qoriq_sensor *sensor = &qdata->sensor[id];
15011ef00f7SAndrey Smirnov int ret;
15111ef00f7SAndrey Smirnov
152d6fb0564SAndrey Smirnov sensor->id = id;
15311ef00f7SAndrey Smirnov
1543e7494b4SDaniel Lezcano tzd = devm_thermal_of_zone_register(dev, id,
155d6fb0564SAndrey Smirnov sensor,
15611ef00f7SAndrey Smirnov &tmu_tz_ops);
15711ef00f7SAndrey Smirnov ret = PTR_ERR_OR_ZERO(tzd);
15811ef00f7SAndrey Smirnov if (ret) {
15911ef00f7SAndrey Smirnov if (ret == -ENODEV)
1607797ff42SYuantian Tang continue;
16145038e03SAndrey Smirnov
16211ef00f7SAndrey Smirnov return ret;
16343528445SJia Hongtao }
164fd843309SAndrey Smirnov
1659301575dSPeng Fan if (qdata->ver == TMU_VER1)
1669301575dSPeng Fan sites |= 0x1 << (15 - id);
1679301575dSPeng Fan else
1689301575dSPeng Fan sites |= 0x1 << id;
1699301575dSPeng Fan
170f13582a4SYangtao Li devm_thermal_add_hwmon_sysfs(dev, tzd);
1719301575dSPeng Fan }
172fd843309SAndrey Smirnov
1739301575dSPeng Fan if (sites) {
1749301575dSPeng Fan if (qdata->ver == TMU_VER1) {
1759301575dSPeng Fan regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF | sites);
1769301575dSPeng Fan } else {
1779301575dSPeng Fan regmap_write(qdata->regmap, REGS_V2_TMSR, sites);
1789301575dSPeng Fan regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF_V2);
1799301575dSPeng Fan }
1809809797bSYuantian Tang }
18143528445SJia Hongtao
1827797ff42SYuantian Tang return 0;
18343528445SJia Hongtao }
18443528445SJia Hongtao
qoriq_tmu_calibration(struct device * dev,struct qoriq_tmu_data * data)1858e1cda35SAndrey Smirnov static int qoriq_tmu_calibration(struct device *dev,
1868e1cda35SAndrey Smirnov struct qoriq_tmu_data *data)
18743528445SJia Hongtao {
18843528445SJia Hongtao int i, val, len;
18943528445SJia Hongtao const u32 *calibration;
1908e1cda35SAndrey Smirnov struct device_node *np = dev->of_node;
19143528445SJia Hongtao
1929809797bSYuantian Tang len = of_property_count_u32_elems(np, "fsl,tmu-range");
193*2584d6bbSPeng Fan if (len < 0 || (data->ver == TMU_VER1 && len > NUM_TTRCR_V1) ||
194*2584d6bbSPeng Fan (data->ver > TMU_VER1 && len > NUM_TTRCR_MAX)) {
1958e1cda35SAndrey Smirnov dev_err(dev, "invalid range data.\n");
1969809797bSYuantian Tang return len;
1979809797bSYuantian Tang }
1989809797bSYuantian Tang
199*2584d6bbSPeng Fan val = of_property_read_u32_array(np, "fsl,tmu-range", data->ttrcr, len);
2009809797bSYuantian Tang if (val != 0) {
2018e1cda35SAndrey Smirnov dev_err(dev, "failed to read range data.\n");
2029809797bSYuantian Tang return val;
20343528445SJia Hongtao }
20443528445SJia Hongtao
20543528445SJia Hongtao /* Init temperature range registers */
2069809797bSYuantian Tang for (i = 0; i < len; i++)
207*2584d6bbSPeng Fan regmap_write(data->regmap, REGS_TTRnCR(i), data->ttrcr[i]);
20843528445SJia Hongtao
20943528445SJia Hongtao calibration = of_get_property(np, "fsl,tmu-calibration", &len);
21043528445SJia Hongtao if (calibration == NULL || len % 8) {
2118e1cda35SAndrey Smirnov dev_err(dev, "invalid calibration data.\n");
21243528445SJia Hongtao return -ENODEV;
21343528445SJia Hongtao }
21443528445SJia Hongtao
21543528445SJia Hongtao for (i = 0; i < len; i += 8, calibration += 2) {
21643528445SJia Hongtao val = of_read_number(calibration, 1);
2174316237bSAndrey Smirnov regmap_write(data->regmap, REGS_TTCFGR, val);
21843528445SJia Hongtao val = of_read_number(calibration + 1, 1);
2194316237bSAndrey Smirnov regmap_write(data->regmap, REGS_TSCFGR, val);
22043528445SJia Hongtao }
22143528445SJia Hongtao
22243528445SJia Hongtao return 0;
22343528445SJia Hongtao }
22443528445SJia Hongtao
qoriq_tmu_init_device(struct qoriq_tmu_data * data)22543528445SJia Hongtao static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
22643528445SJia Hongtao {
22743528445SJia Hongtao /* Disable interrupt, using polling instead */
2284316237bSAndrey Smirnov regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
22943528445SJia Hongtao
23043528445SJia Hongtao /* Set update_interval */
2314316237bSAndrey Smirnov
2329809797bSYuantian Tang if (data->ver == TMU_VER1) {
2334316237bSAndrey Smirnov regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
2349809797bSYuantian Tang } else {
2354316237bSAndrey Smirnov regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
2364316237bSAndrey Smirnov regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
2379809797bSYuantian Tang }
23843528445SJia Hongtao
23943528445SJia Hongtao /* Disable monitoring */
2404316237bSAndrey Smirnov regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
24143528445SJia Hongtao }
24243528445SJia Hongtao
2434316237bSAndrey Smirnov static const struct regmap_range qoriq_yes_ranges[] = {
2444316237bSAndrey Smirnov regmap_reg_range(REGS_TMR, REGS_TSCFGR),
245f12d60c8SPeng Fan regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(15)),
2464316237bSAndrey Smirnov regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
24747fa116eSYuantian Tang regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)),
2484316237bSAndrey Smirnov regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
2494316237bSAndrey Smirnov /* Read only registers below */
2504316237bSAndrey Smirnov regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
2514316237bSAndrey Smirnov };
2524316237bSAndrey Smirnov
2534316237bSAndrey Smirnov static const struct regmap_access_table qoriq_wr_table = {
2544316237bSAndrey Smirnov .yes_ranges = qoriq_yes_ranges,
2554316237bSAndrey Smirnov .n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges) - 1,
2564316237bSAndrey Smirnov };
2574316237bSAndrey Smirnov
2584316237bSAndrey Smirnov static const struct regmap_access_table qoriq_rd_table = {
2594316237bSAndrey Smirnov .yes_ranges = qoriq_yes_ranges,
2604316237bSAndrey Smirnov .n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges),
2614316237bSAndrey Smirnov };
2624316237bSAndrey Smirnov
qoriq_tmu_action(void * p)26385f0b61aSAnson Huang static void qoriq_tmu_action(void *p)
26485f0b61aSAnson Huang {
26585f0b61aSAnson Huang struct qoriq_tmu_data *data = p;
26685f0b61aSAnson Huang
26785f0b61aSAnson Huang regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
26885f0b61aSAnson Huang clk_disable_unprepare(data->clk);
26985f0b61aSAnson Huang }
27085f0b61aSAnson Huang
qoriq_tmu_probe(struct platform_device * pdev)27143528445SJia Hongtao static int qoriq_tmu_probe(struct platform_device *pdev)
27243528445SJia Hongtao {
27343528445SJia Hongtao int ret;
2749809797bSYuantian Tang u32 ver;
27543528445SJia Hongtao struct qoriq_tmu_data *data;
27643528445SJia Hongtao struct device_node *np = pdev->dev.of_node;
277e167dc43SAndrey Smirnov struct device *dev = &pdev->dev;
2784316237bSAndrey Smirnov const bool little_endian = of_property_read_bool(np, "little-endian");
2794316237bSAndrey Smirnov const enum regmap_endian format_endian =
2804316237bSAndrey Smirnov little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
2814316237bSAndrey Smirnov const struct regmap_config regmap_config = {
2824316237bSAndrey Smirnov .reg_bits = 32,
2834316237bSAndrey Smirnov .val_bits = 32,
2844316237bSAndrey Smirnov .reg_stride = 4,
2854316237bSAndrey Smirnov .rd_table = &qoriq_rd_table,
2864316237bSAndrey Smirnov .wr_table = &qoriq_wr_table,
2874316237bSAndrey Smirnov .val_format_endian = format_endian,
2884316237bSAndrey Smirnov .max_register = SZ_4K,
2894316237bSAndrey Smirnov };
2904316237bSAndrey Smirnov void __iomem *base;
29143528445SJia Hongtao
292e167dc43SAndrey Smirnov data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
29343528445SJia Hongtao GFP_KERNEL);
29443528445SJia Hongtao if (!data)
29543528445SJia Hongtao return -ENOMEM;
29643528445SJia Hongtao
2974316237bSAndrey Smirnov base = devm_platform_ioremap_resource(pdev, 0);
2984316237bSAndrey Smirnov ret = PTR_ERR_OR_ZERO(base);
2994316237bSAndrey Smirnov if (ret) {
300e167dc43SAndrey Smirnov dev_err(dev, "Failed to get memory region\n");
3014316237bSAndrey Smirnov return ret;
3024316237bSAndrey Smirnov }
3034316237bSAndrey Smirnov
3044316237bSAndrey Smirnov data->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
3054316237bSAndrey Smirnov ret = PTR_ERR_OR_ZERO(data->regmap);
3064316237bSAndrey Smirnov if (ret) {
3074316237bSAndrey Smirnov dev_err(dev, "Failed to init regmap (%d)\n", ret);
3084316237bSAndrey Smirnov return ret;
30943528445SJia Hongtao }
31043528445SJia Hongtao
311e167dc43SAndrey Smirnov data->clk = devm_clk_get_optional(dev, NULL);
31251904045SAnson Huang if (IS_ERR(data->clk))
31351904045SAnson Huang return PTR_ERR(data->clk);
31451904045SAnson Huang
31551904045SAnson Huang ret = clk_prepare_enable(data->clk);
31651904045SAnson Huang if (ret) {
317e167dc43SAndrey Smirnov dev_err(dev, "Failed to enable clock\n");
31851904045SAnson Huang return ret;
31951904045SAnson Huang }
32051904045SAnson Huang
32185f0b61aSAnson Huang ret = devm_add_action_or_reset(dev, qoriq_tmu_action, data);
32285f0b61aSAnson Huang if (ret)
32385f0b61aSAnson Huang return ret;
32485f0b61aSAnson Huang
3259809797bSYuantian Tang /* version register offset at: 0xbf8 on both v1 and v2 */
3264316237bSAndrey Smirnov ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
3274316237bSAndrey Smirnov if (ret) {
3284316237bSAndrey Smirnov dev_err(&pdev->dev, "Failed to read IP block version\n");
3294316237bSAndrey Smirnov return ret;
3304316237bSAndrey Smirnov }
3319809797bSYuantian Tang data->ver = (ver >> 8) & 0xff;
3329809797bSYuantian Tang
33343528445SJia Hongtao qoriq_tmu_init_device(data); /* TMU initialization */
33443528445SJia Hongtao
3358e1cda35SAndrey Smirnov ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */
33643528445SJia Hongtao if (ret < 0)
33785f0b61aSAnson Huang return ret;
33843528445SJia Hongtao
33903036625SAndrey Smirnov ret = qoriq_tmu_register_tmu_zone(dev, data);
3407797ff42SYuantian Tang if (ret < 0) {
341e167dc43SAndrey Smirnov dev_err(dev, "Failed to register sensors\n");
34243528445SJia Hongtao return ret;
34343528445SJia Hongtao }
34443528445SJia Hongtao
34585f0b61aSAnson Huang platform_set_drvdata(pdev, data);
34651904045SAnson Huang
34743528445SJia Hongtao return 0;
34843528445SJia Hongtao }
34943528445SJia Hongtao
qoriq_tmu_suspend(struct device * dev)350aea59197SAnson Huang static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
35143528445SJia Hongtao {
35243528445SJia Hongtao struct qoriq_tmu_data *data = dev_get_drvdata(dev);
3534316237bSAndrey Smirnov int ret;
35443528445SJia Hongtao
3554316237bSAndrey Smirnov ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
3564316237bSAndrey Smirnov if (ret)
3574316237bSAndrey Smirnov return ret;
35843528445SJia Hongtao
35951904045SAnson Huang clk_disable_unprepare(data->clk);
36051904045SAnson Huang
36143528445SJia Hongtao return 0;
36243528445SJia Hongtao }
36343528445SJia Hongtao
qoriq_tmu_resume(struct device * dev)364aea59197SAnson Huang static int __maybe_unused qoriq_tmu_resume(struct device *dev)
36543528445SJia Hongtao {
36651904045SAnson Huang int ret;
36743528445SJia Hongtao struct qoriq_tmu_data *data = dev_get_drvdata(dev);
36843528445SJia Hongtao
36951904045SAnson Huang ret = clk_prepare_enable(data->clk);
37051904045SAnson Huang if (ret)
37151904045SAnson Huang return ret;
37251904045SAnson Huang
37343528445SJia Hongtao /* Enable monitoring */
3744316237bSAndrey Smirnov return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
37543528445SJia Hongtao }
37643528445SJia Hongtao
37743528445SJia Hongtao static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
37843528445SJia Hongtao qoriq_tmu_suspend, qoriq_tmu_resume);
37943528445SJia Hongtao
38043528445SJia Hongtao static const struct of_device_id qoriq_tmu_match[] = {
38143528445SJia Hongtao { .compatible = "fsl,qoriq-tmu", },
3826017e2a9SAnson Huang { .compatible = "fsl,imx8mq-tmu", },
38343528445SJia Hongtao {},
38443528445SJia Hongtao };
38543528445SJia Hongtao MODULE_DEVICE_TABLE(of, qoriq_tmu_match);
38643528445SJia Hongtao
38743528445SJia Hongtao static struct platform_driver qoriq_tmu = {
38843528445SJia Hongtao .driver = {
38943528445SJia Hongtao .name = "qoriq_thermal",
39043528445SJia Hongtao .pm = &qoriq_tmu_pm_ops,
39143528445SJia Hongtao .of_match_table = qoriq_tmu_match,
39243528445SJia Hongtao },
39343528445SJia Hongtao .probe = qoriq_tmu_probe,
39443528445SJia Hongtao };
39543528445SJia Hongtao module_platform_driver(qoriq_tmu);
39643528445SJia Hongtao
39743528445SJia Hongtao MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
39843528445SJia Hongtao MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
39943528445SJia Hongtao MODULE_LICENSE("GPL v2");
400