Searched +full:tlb +full:- +full:split (Results 1 – 25 of 30) sorted by relevance
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5 -----------11 -----17 - ``kvmclock``18 - ``kvm-nopiodelay``19 - ``kvm-asyncpf``20 - ``kvm-steal-time``21 - ``kvm-pv-eoi``22 - ``kvmclock-stable-bit``24 ``kvm-msi-ext-dest-id`` feature is enabled by default in x2apic mode with split25 irqchip (e.g. "-machine ...,kernel-irqchip=split -cpu ...,x2apic").[all …]
2 * QEMU RISC-V PMP (Physical Memory Protection)7 * This provides a RISC-V Physical Memory Protection implementation28 #include "exec/page-protection.h"58 if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) { in pmp_is_locked()85 * Adding a rule with executable privileges that either is M-mode-only in pmp_is_invalid_smepmp_cfg()86 * or a locked Shared-Region is not possible in pmp_is_invalid_smepmp_cfg()117 return env->pmp_state.num_rules; in pmp_get_num_rules()125 uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions; in pmp_read_cfg()128 return env->pmp_state.pmp[pmp_index].cfg_reg; in pmp_read_cfg()141 uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions; in pmp_write_cfg()[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */3 * QEMU LoongArch TLB helpers10 #include "qemu/guest-random.h"14 #include "exec/helper-proto.h"16 #include "exec/page-protection.h"18 #include "accel/tcg/cpu-ldst.h"20 #include "cpu-csr.h"28 return BIT_ULL(tlb_ps) & (env->CSR_PRCFG2); in check_ps()39 cs->exception_index = access_type == MMU_INST_FETCH in raise_mmu_exception()43 /* No TLB match for a mapped address */ in raise_mmu_exception()[all …]
2 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.30 #include "qemu/qemu-print.h"33 #include "exec/helper-proto.h"34 #include "qemu/host-utils.h"36 #include "accel/tcg/cpu-mmu-index.h"38 #include "exec/page-protection.h"71 * only the side-effects (ie any MMU or other exception) in HELPER()80 if (v != env->sregs[RASID]) { in HELPER()81 env->sregs[RASID] = v; in HELPER()89 uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; in get_page_size()[all …]
18 * <http://www.gnu.org/licenses/gpl-2.0.html>23 #include "hw/qdev-core.h"24 #include "disas/dis-asm.h"29 #include "exec/mmu-access-type.h"30 #include "exec/tlb-common.h"31 #include "qapi/qapi-types-machine.h"32 #include "qapi/qapi-types-run-state.h"45 * @section_id: QEMU-cpu62 * has a cached value for the class in cs->cc which is set up in75 * This macro is typically used in "cpu-qom.h" header file, and will:[all …]
23 #include "tcg/tcg-gvec-desc.h"24 #include "exec/helper-proto.h"25 #include "accel/tcg/cpu-ldst.h"26 #include "accel/tcg/helper-retaddr.h"54 memset(env->za_state.za, 0, sizeof(env->za_state.za)); in helper_sme_zero()64 memset(&env->za_state.za[i], 0, svl); in helper_sme_zero()78 * by N to convert from vslice-index-within-the-tile to92 * at offset (8 * row-size-in-bytes).97 * (8 * row-size-in-bytes). Similarly for other element sizes.449 * Host and TLB primitives for vertical tile slice addressing.[all …]
23 #include "exec/page-protection.h"24 #include "exec/helper-proto.h"26 #include "exec/tlb-flags.h"27 #include "tcg/tcg-gvec-desc.h"32 #include "accel/tcg/cpu-ldst.h"33 #include "accel/tcg/helper-retaddr.h"34 #include "accel/tcg/cpu-ops.h"37 #include "user/page-protection.h"60 flags |= ((d & (g & -g)) != 0) << 31; in iter_predtest_fwd()82 flags += 4 - 1; /* add bit 2, subtract C from PREDTEST_INIT */ in iter_predtest_bwd()[all …]
4 * Copyright (c) 2003-2005 Fabrice Bellard25 #include "exec/helper-proto.h"27 #include "exec/page-protection.h"29 #include "accel/tcg/cpu-ldst.h"32 #include "user/page-protection.h"70 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)87 int ctx = mmu->tag_access & 0x1fffULL; in ultrasparc_tsb_pointer()88 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; in ultrasparc_tsb_pointer()93 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; in ultrasparc_tsb_pointer()96 tsb_register = mmu->tsb; in ultrasparc_tsb_pointer()[all …]
4 * Copyright (c) 2003-2007 Jocelyn Mayer24 #include "qemu/cpu-float.h"25 #include "exec/cpu-common.h"26 #include "exec/cpu-defs.h"27 #include "exec/cpu-interrupt.h"28 #include "cpu-qom.h"43 #define PPC_BIT_NR(bit) (63 - (bit))45 #define PPC_BIT32_NR(bit) (31 - (bit))48 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))49 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \[all …]
4 * Copyright (c) 2018-2021 BALATON Zoltan17 #include "hw/or-irq.h"18 #include "hw/pci-host/mv64361.h"22 #include "hw/qdev-properties.h"28 #include "hw/fw-path-provider.h"31 #include "qemu/error-report.h"34 #include "system/address-spaces.h"35 #include "qom/qom-qobject.h"55 #define H_PRIVILEGE -3 /* Caller not privileged */56 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */[all …]
10 #include "mmu-book3s-v3.h"11 #include "cpu-models.h"20 spapr->nested.capabilities_set = false; in spapr_nested_reset()25 spapr->nested.api = 0; in spapr_nested_reset()31 return spapr->nested.api; in spapr_nested_api()43 patb = spapr->nested.ptcr & PTCR_PATB; in spapr_get_pate_nested_hv()44 pats = spapr->nested.ptcr & PTCR_PATS; in spapr_get_pate_nested_hv()52 pats = 1ull << (pats + 12 - 4); in spapr_get_pate_nested_hv()59 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); in spapr_get_pate_nested_hv()60 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); in spapr_get_pate_nested_hv()[all …]
13 #include <libcper/cper-utils.h>14 #include <libcper/sections/cper-section-arm.h>19 //Private pre-definitions.50 //Converts the given processor-generic CPER section into JSON IR.74 remaining_size -= sizeof(EFI_ARM_ERROR_RECORD); in cper_section_arm_to_ir()79 .value.ui64 = record->ValidFields }; in cper_section_arm_to_ir()83 json_object_new_int(record->ErrInfoNum)); in cper_section_arm_to_ir()85 json_object_new_int(record->ContextInfoNum)); in cper_section_arm_to_ir()87 json_object_new_uint64(record->SectionLength)); in cper_section_arm_to_ir()94 json_object_new_int(record->ErrorAffinityLevel)); in cper_section_arm_to_ir()[all …]
12 #include <libcper/cper-utils.h>13 #include <libcper/sections/cper-section-ia32x64.h>17 //Private pre-definitions.70 size - sizeof(EFI_IA32_X64_PROCESSOR_ERROR_RECORD); in cper_section_ia32x64_to_ir()76 //Ensure this is decoded properly in IR->CPER in cper_section_ia32x64_to_ir()77 int processor_error_info_num = (record->ValidFields >> 2) & 0x3F; in cper_section_ia32x64_to_ir()80 int processor_context_info_num = (record->ValidFields >> 8) & 0x3F; in cper_section_ia32x64_to_ir()85 .value.ui64 = record->ValidFields }; in cper_section_ia32x64_to_ir()90 json_object_new_uint64(record->ApicId)); in cper_section_ia32x64_to_ir()97 (EFI_IA32_X64_CPU_ID *)record->CpuIdInfo; in cper_section_ia32x64_to_ir()[all …]
23 #include "cpu-qom.h"24 #include "exec/cpu-common.h"25 #include "exec/cpu-defs.h"26 #include "exec/cpu-interrupt.h"27 #include "qemu/cpu-float.h"145 uint32_t sr; /* status register (with T split out) */183 uint32_t tea; /* TLB exception address register */191 /* LDST = LOCK_ADDR != -1. */297 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)306 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)[all …]
23 #include "kvm-consts.h"24 #include "qemu/cpu-float.h"26 #include "cpu-qom.h"27 #include "exec/cpu-common.h"28 #include "exec/cpu-defs.h"29 #include "exec/cpu-interrupt.h"31 #include "exec/page-protection.h"32 #include "qapi/qapi-types-common.h"35 #include "target/arm/cpu-sysregs.h"79 /* ARM-specific interrupt pending bits. */[all …]
18 ----------------43 have some non-deterministic state they want to reinitialize to a different45 must not reinitialize on a snapshot-load reset.49 its devices during wake-up (from the ``MachineClass::wakeup()`` method), this51 type to differentiate the reset requested during machine wake-up from other52 reset requests. For example, RAM content must not be lost during wake-up, and53 memory devices like virtio-mem that provide additional RAM must not reset54 such state during wake-ups, but might do so during cold resets. However, this55 reset type should not be used for wake-up detection, as not every machine56 type issues a device reset request during wake-up.[all …]
1 .. _tcg-ops-ref:43 a sequence of basic blocks connected by the fall-through paths of60 .. code-block:: none62 add_i32 t0, t1, t2 /* (t0 <- t1 + t2) */109 A 32-bit integer.113 A 64-bit integer. For 32-bit hosts, such variables are split into a pair116 host-endian representation.131 A 128-bit integer. For all hosts, such variables are split into a number134 host-endian representation.138 A 64-bit vector. This type is valid only if the TCG target[all …]
4 * Copyright (c) 2003-2005 Fabrice Bellard20 #include "accel/tcg/cpu-ops.h"23 #include "exec/tlb-flags.h"27 #include "accel/tcg/cpu-ldst-common.h"28 #include "accel/tcg/helper-retaddr.h"31 #include "user/guest-host.h"32 #include "qemu/main-loop.h"33 #include "user/page-protection.h"34 #include "exec/page-protection.h"35 #include "exec/helper-proto-common.h"[all …]
2 * Copyright (C) 2014-2016 Broadcom Corporation24 #include "hw/qdev-properties.h"25 #include "hw/qdev-core.h"31 #include "qemu/error-report.h"35 #include "smmuv3-internal.h"36 #include "smmu-internal.h"39 (cfg)->record_faults) || \41 (cfg)->s2cfg.record_faults))44 * smmuv3_trigger_irq - pulse @irq if enabled and update68 uint32_t pending = s->gerror ^ s->gerrorn; in smmuv3_trigger_irq()[all …]
1 // SPDX-License-Identifier: GPL-2.0+4 * Copyright 2014-2015 Freescale Semiconductor, Inc.22 #include <fsl-mc/fsl_mc.h>86 /* For IFC Region #1, only the first 4MB is cache-enabled */93 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,114 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,227 /* For QBMAN portal, only the first 64MB is cache-enabled */235 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,368 svr = gur_in32(&gur->svr); in cpu_name()395 * levels of translation tables here to cover 40-bit address space.[all …]
... i-cache-sets d-cache-block-size i-cache-block-size tlb- ...
4 * Copyright (C) 2006-2008 Qumranet Technologies11 * See the COPYING file in the top-level directory.16 #include "qapi/qapi-events-run-state.h"28 #include "standard-headers/asm-x86/kvm_para.h"29 #include "hw/xen/interface/arch-x86/cpuid.h"32 #include "host-cpu.h"39 #include "../confidential-guest.h"42 #include "xen-emu.h"44 #include "hyperv-proto.h"47 #include "qemu/host-utils.h"[all …]
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */37 /* Two-stage IOMMU */43 * The No-IOMMU IOMMU offers no translation or isolation for devices and44 * supports no ioctls outside of VFIO_CHECK_EXTENSION. Use of VFIO's No-IOMMU100 /* -------- IOCTLs for VFIO file descriptor (/dev/vfio/vfio) -------- */103 * VFIO_GET_API_VERSION - _IO(VFIO_TYPE, VFIO_BASE + 0)114 * VFIO_CHECK_EXTENSION - _IOW(VFIO_TYPE, VFIO_BASE + 1, __u32)123 * VFIO_SET_IOMMU - _IOW(VFIO_TYPE, VFIO_BASE + 2, __s32)130 * Return: 0 on success, -errno on failure135 /* -------- IOCTLs for GROUP file descriptors (/dev/vfio/$GROUP) -------- */[all …]
23 #include "qemu/qemu-print.h"24 #include "qemu/hw-version.h"26 #include "tcg/helper-tcg.h"27 #include "exec/translation-block.h"29 #include "hvf/hvf-i386.h"34 #include "qemu/error-report.h"35 #include "qapi/qapi-visit-machine.h"36 #include "standard-headers/asm-x86/kvm_para.h"37 #include "hw/qdev-properties.h"41 #include "confidential-guest.h"[all …]
30 #include "qemu/error-report.h"32 #include "qemu/host-utils.h"33 #include "qemu/qemu-print.h"38 #include "exec/translation-block.h"39 #include "exec/tlb-common.h"41 #include "tcg/tcg-op-common.h"56 #include "tcg/tcg-ldst.h"57 #include "tcg/tcg-temp-internal.h"58 #include "tcg-internal.h"60 #include "tcg-has.h"[all …]