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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dxlnx,xps-timer.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx LogiCORE IP AXI Timer
10 - Sean Anderson <sean.anderson@seco.com>
15 const: xlnx,xps-timer-1.00.a
20 clock-names:
29 '#pwm-cells': true
31 xlnx,count-width:
[all …]
H A Dcdns,ttc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/cdns,ttc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence TTC - Triple Timer Counter
10 - Michal Simek <michal.simek@amd.com>
22 A list of 3 interrupts; one per timer channel.
27 power-domains:
30 timer-width:
33 Bit width of the timer, necessary if not 16.
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H A Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Low Power Timer/Pulse Width Modulation Module (TPM)
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The Timer/PWM Module (TPM) supports input capture, output compare,
18 the counter bus for the others, provided bit width is the same.
23 - const: fsl,imx7ulp-tpm
24 - items:
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/openbmc/qemu/hw/m68k/
H A Dmcf5206.c10 #include "qemu/error-report.h"
13 #include "hw/qdev-properties.h"
17 #include "qemu/timer.h"
22 /* General purpose timer module. */
28 ptimer_state *timer; member
45 if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF)) in m5206_timer_update()
46 qemu_irq_raise(s->irq); in m5206_timer_update()
48 qemu_irq_lower(s->irq); in m5206_timer_update()
53 s->tmr = 0; in m5206_timer_reset()
54 s->trr = 0; in m5206_timer_reset()
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/openbmc/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
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/openbmc/linux/drivers/clocksource/
H A Dtimer-sp804.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/clocksource/timer-sp.c
5 * Copyright (C) 1999 - 2003 ARM Limited
24 #include "timer-sp.h"
26 /* Hisilicon 64-bit timer(a variant of ARM SP804) */
46 .width = 32,
57 .width = 64,
102 return ~readl_relaxed(sched_clkevt->value); in sp804_read()
115 return -EINVAL; in sp804_clocksource_and_sched_clock_init()
119 writel(0, clkevt->ctrl); in sp804_clocksource_and_sched_clock_init()
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H A Dtimer-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Inspired by time-efm32.c from Uwe Kleine-Koenig
23 #include "timer-of.h"
54 * stm32_timer_of_bits_set - set accessor helper
58 * Accessor helper to set the number of bits in the timer-of private
64 struct stm32_timer_private *pd = to->private_data; in stm32_timer_of_bits_set()
66 pd->bits = bits; in stm32_timer_of_bits_set()
70 * stm32_timer_of_bits_get - get accessor helper
73 * Accessor helper to get the number of bits in the timer-of private
80 struct stm32_timer_private *pd = to->private_data; in stm32_timer_of_bits_get()
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/openbmc/linux/drivers/pwm/
H A Dpwm-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
6 * - When changing both duty cycle and period, we may end up with one cycle
13 * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
16 * - Only produces "normal" output.
17 * - Always produces low output if disabled.
20 #include <clocksource/timer-xilinx.h>
22 #include <linux/clk-provider.h>
37 WARN_ON(cycles < 2 || cycles - 2 > priv->max); in xilinx_timer_tlr_cycles()
40 return cycles - 2; in xilinx_timer_tlr_cycles()
41 return priv->max - cycles + 2; in xilinx_timer_tlr_cycles()
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H A Dpwm-dwc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2020 Intel Corporation
12 * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low
39 /* Timer Control Register */
62 return readl(dwc->base + offset); in dwc_pwm_readl()
67 writel(value, dwc->base + offset); in dwc_pwm_writel()
94 * Calculate width of low and high period in terms of input clock in __dwc_pwm_configure_timer()
98 tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); in __dwc_pwm_configure_timer()
100 return -ERANGE; in __dwc_pwm_configure_timer()
101 low = tmp - 1; in __dwc_pwm_configure_timer()
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/openbmc/openbmc/poky/bitbake/lib/progressbar/
H A Dwidgets.py1 # -*- coding: utf-8 -*-
3 # progressbar - Text progress bar library for Python.
6 # SPDX-License-Identifier: LGPL-2.1-or-later OR BSD-3-Clause-Clear
20 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
61 pbar - a reference to the calling ProgressBar
66 """The base class for all variable width widgets.
70 all have the same width, and together will fill the line.
74 def update(self, pbar, width): argument
75 """Updates the widget providing the total width the widget must fill.
77 pbar - a reference to the calling ProgressBar
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/openbmc/qemu/hw/block/
H A Dpflash_cfi02.c21 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * - flash read
24 * - flash write
25 * - flash ID read
26 * - sector erase
27 * - chip erase
28 * - unlock bypass command
29 * - CFI queries
38 #include "hw/qdev-properties.h"
39 #include "hw/qdev-properties-system.h"
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/openbmc/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
28 * Since this is a non-ratified draft specification, the kernel does not
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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721s2-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-j784s4-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 bootph-all;
11 compatible = "ti,k2g-sci";
12 ti,host-id = <12>;
14 mbox-names = "rx", "tx";
19 reg-names = "debug_messages";
22 k3_pds: power-controller {
23 bootph-all;
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H A Dk3-j7200-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A DMC68328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
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H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
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H A DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
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/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
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/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-sam9_l9260.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-sam9_l9260.dts - Device Tree file for Olimex SAM9-L9260 board
7 /dts-v1/;
11 model = "Olimex sam9-l9260";
12 compatible = "olimex,sam9-l9260", "atmel,at91sam9260", "atmel,at91sam9";
15 stdout-path = "serial0:115200n8";
24 clock-frequency = <32768>;
28 clock-frequency = <18432000>;
34 tcb0: timer@fffa0000 {
35 timer@0 {
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H A Dat91sam9260ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
17 stdout-path = &dbgu;
26 clock-frequency = <32768>;
30 clock-frequency = <18432000>;
36 tcb0: timer@fffa0000 {
37 timer@0 {
38 compatible = "atmel,tcb-timer";
42 timer@2 {
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/openbmc/linux/arch/arm64/boot/dts/amazon/
H A Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
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/openbmc/u-boot/arch/nios2/dts/
H A D3c120_devboard.dts1 // SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "altr,nios2-1.0";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 clock-frequency = <125000000>;
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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsnps,dwcmshc-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
14 - $ref: mmc-controller.yaml#
19 - rockchip,rk3568-dwcmshc
20 - rockchip,rk3588-dwcmshc
21 - snps,dwcmshc-sdhci
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53", "arm,armv8";
27 enable-method = "psci";
28 operating-points-v2 = <&cpu_opp_table>;
30 cpu-idle-states = <&CPU_SLEEP_0>;
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