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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dnvidia,tegra-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra timer
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
25 A list of 14 interrupts; one per each timer channels 0 through 13
27 - if:
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra30.dtsi1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra30-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 compatible = "nvidia,tegra30";
11 interrupt-parent = <&lic>;
13 pcie-controller@00003000 {
14 compatible = "nvidia,tegra30-pcie";
19 reg-names = "pads", "afi", "cs";
[all …]
H A Dtegra114.dtsi1 #include <dt-bindings/clock/tegra114-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra114-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&lic>;
14 compatible = "nvidia,tegra114-host1x", "simple-bus";
20 reset-names = "host1x";
22 #address-cells = <1>;
23 #size-cells = <1>;
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H A Dtegra124.dtsi1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
14 interrupt-parent = <&lic>;
17 pcie-controller@01003000 {
[all …]
H A Dtegra210.dtsi1 #include <dt-bindings/clock/tegra210-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra210-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
10 interrupt-parent = <&lic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 pcie-controller@01003000 {
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
13 compatible = "nvidia,tegra30";
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H A Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
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H A Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
19 - nvidia,tegra124-usb-phy
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/openbmc/linux/drivers/clocksource/
H A Dtimer-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #define pr_fmt(fmt) "tegra-timer: " fmt
24 #include "timer-of.h"
60 * Tegra's timer uses n+1 scheme for the counter, i.e. timer will in tegra_timer_set_next_event()
68 writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV); in tegra_timer_set_next_event()
87 writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1), in tegra_timer_set_periodic()
99 evt->event_handler(evt); in tegra_timer_isr()
139 irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); in tegra_timer_setup()
140 enable_irq(to->clkevt.irq); in tegra_timer_setup()
143 * Tegra's timer uses n+1 scheme for the counter, i.e. timer will in tegra_timer_setup()
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/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
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H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dnvidia,tegra20-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra real-time clock
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 from low-power state.
21 - const: nvidia,tegra20-rtc
22 - items:
[all …]
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/tegra30-car.h>
21 #include "clk-id.h"
595 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
596 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
597 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
601 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
602 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
604 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
[all …]
/openbmc/linux/drivers/watchdog/
H A Dtegra_wdt.c1 // SPDX-License-Identifier: GPL-2.0
19 * Base of the WDT registers, from the timer base address. There are
21 * timer), at bases 0x100 + (WDT ID) * 0x20, where WDT ID is 0 through 4.
28 * Register base of the timer that's selected for pairing with the watchdog.
29 * This driver arbitrarily uses timer 5, which is currently unused by
31 * needs to change, take care that the new timer is not used by the
54 /* Timer registers */
91 writel(val, wdt->tmr_regs + TIMER_PTV); in tegra_wdt_start()
101 (wdd->timeout << WDT_CFG_PERIOD_SHIFT) | in tegra_wdt_start()
103 writel(val, wdt->wdt_regs + WDT_CFG); in tegra_wdt_start()
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
7 /* Tegra30 Clock control functions */
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
20 * Clock types that we can use as a source. The Tegra30 has muxes for the
47 CLOCK_TYPE_NONE = -1, /* invalid clock type */
141 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
175 /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
220 * SPDIF - which is both 0x08 and 0x0c
[all …]
/openbmc/linux/drivers/input/keyboard/
H A Dtegra-kbc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (c) 2009-2011, NVIDIA Corporation.
104 struct timer_list timer; member
156 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i); in tegra_kbc_report_keys()
165 keycodes[num_down] = kbc->keycode[scancode]; in tegra_kbc_report_keys()
167 if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map) in tegra_kbc_report_keys()
178 * Ghosting occurs if there are 3 keys such that - in tegra_kbc_report_keys()
182 if (kbc->use_ghost_filter && num_down >= 3) { in tegra_kbc_report_keys()
190 * and the other is in the same column as the i-th key. in tegra_kbc_report_keys()
210 scancodes[i] += kbc->max_keys; in tegra_kbc_report_keys()
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
15 #include <asm/arch-tegra/ap.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/timer.h>
66 reg = readl(&clkrst->crc_osc_ctrl); in clock_get_osc_bypass()
81 return &clkrst->crc_pll[clkid]; in get_pll()
100 return -1; in clock_ll_read_pll()
101 data = readl(&pll->pll_base); in clock_ll_read_pll()
[all …]
/openbmc/u-boot/tools/buildman/
H A DREADME1 # SPDX-License-Identifier: GPL-2.0+
6 Quick-start
12 cd /path/to/u-boot
14 buildman --fetch-arch arm
15 buildman -k rpi_2
17 # u-boot.bin is the output image
23 This tool handles building U-Boot to check that you have not broken it
26 to make full use of multi-processor machines.
38 where it left off. This should happen cleanly and without side-effects.
42 You may need to press Ctrl-C several times to quit it. Also it will print
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2015
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
49 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
57 CLOCK_TYPE_NONE = -1, /* invalid clock type */
122 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
320 * SPDIF - which is both 0x08 and 0x0c
323 #define NONE(name) (-1)
601 * field. Note that Tegra30+ support 3 new higher freqs, but we map back
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2015
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
50 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
59 CLOCK_TYPE_NONE = -1, /* invalid clock type */
124 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
350 * SPDIF - which is both 0x08 and 0x0c
353 #define NONE(name) (-1)
597 /* Y: 192 (192 - 223) */
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
43 stats->frames = 0; in tegra_dc_stats_reset()
44 stats->vblank = 0; in tegra_dc_stats_reset()
45 stats->underflow = 0; in tegra_dc_stats_reset()
46 stats->overflow = 0; in tegra_dc_stats_reset()
65 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
66 return plane->offset + offset; in tegra_plane_offset()
70 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
71 return plane->offset + offset; in tegra_plane_offset()
[all …]
/openbmc/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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