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/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dnvidia,tegra20-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra real-time clock
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra RTC maintains seconds and milliseconds counters, and five
16 from low-power state.
21 - const: nvidia,tegra20-rtc
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dnvidia,tegra-regulators-coupling.txt4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
5 Thus on Tegra20 there are 3 coupled regulators and on NVIDIA Tegra30
8 Tegra20 voltage coupling
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
16 ------------------------
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
27 as the "RTC domain" voltage regulator.
[all …]
/openbmc/linux/drivers/clocksource/
H A Dtimer-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #define pr_fmt(fmt) "tegra-timer: " fmt
24 #include "timer-of.h"
68 writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV); in tegra_timer_set_next_event()
87 writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1), in tegra_timer_set_periodic()
99 evt->event_handler(evt); in tegra_timer_isr()
139 irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); in tegra_timer_setup()
140 enable_irq(to->clkevt.irq); in tegra_timer_setup()
150 clockevents_config_and_register(&to->clkevt, timer_of_rate(to), in tegra_timer_setup()
161 to->clkevt.set_state_shutdown(&to->clkevt); in tegra_timer_stop()
[all …]
/openbmc/linux/drivers/soc/tegra/
H A Dregulators-tegra20.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Voltage regulators coupler for NVIDIA Tegra20
4 * Copyright (C) 2019 GRATE-DRIVER project
7 * Copyright (C) 2010-2011 NVIDIA Corporation
10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
53 * Tegra20 SoC has critical DVFS-capable devices that are in tegra20_core_limit()
54 * permanently-active or active at a boot time, like EMC in tegra20_core_limit()
60 * the state of all DVFS-critical CORE devices is synced. in tegra20_core_limit()
62 if (tegra_pmc_core_domain_state_synced() && !tegra->sys_reboot_mode) { in tegra20_core_limit()
67 if (tegra->core_min_uV > 0) in tegra20_core_limit()
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-colibri-iris.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra20-colibri.dtsi"
9 compatible = "toradex,colibri_t20-iris", "toradex,colibri_t20",
10 "nvidia,tegra20";
13 rtc0 = "/i2c@7000c000/rtc@68";
15 rtc2 = "/rtc@7000e000";
22 stdout-path = "serial0:115200n8";
35 hdmi-supply = <&reg_5v0>;
[all …]
H A Dtegra20-colibri-eval-v3.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra20-colibri.dtsi"
9 compatible = "toradex,colibri_t20-eval-v3", "toradex,colibri_t20",
10 "nvidia,tegra20";
13 rtc0 = "/i2c@7000c000/rtc@68";
15 rtc2 = "/rtc@7000e000";
22 stdout-path = "serial0:115200n8";
35 hdmi-supply = <&reg_5v0>;
[all …]
H A Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
12 compatible = "nvidia,tegra20";
13 interrupt-parent = <&lic>;
[all …]
H A Dtegra20-trimslice.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra20.dtsi"
6 #include "tegra20-cpu-opp.dtsi"
10 compatible = "compulab,trimslice", "nvidia,tegra20";
13 rtc0 = "/i2c@7000c500/rtc@56";
14 rtc1 = "/rtc@7000e000";
19 stdout-path = "serial0:115200n8";
30 vdd-supply = <&hdmi_vdd_reg>;
[all …]
H A Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
[all …]
H A Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20.dtsi"
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
13 compatible = "compal,paz00", "nvidia,tegra20";
19 rtc1 = "/rtc@7000e000";
25 stdout-path = "serial0:115200n8";
[all …]
H A Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20.dtsi"
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
15 compatible = "acer,picasso", "nvidia,tegra20";
[all …]
H A Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20.dtsi"
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
15 compatible = "asus,tf101", "nvidia,tegra20";
[all …]
H A Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
6 #include "tegra20.dtsi"
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
11 model = "NVIDIA Tegra20 Ventana evaluation board";
12 compatible = "nvidia,ventana", "nvidia,tegra20";
16 rtc1 = "/rtc@7000e000";
[all …]
H A Dtegra20-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra20.dtsi"
22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
23 nvidia,hpd-gpio =
25 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
26 vdd-supply = <&reg_3v3_avdd_hdmi>;
31 lan-reset-n-hog {
32 gpio-hog;
34 output-high;
35 line-name = "LAN_RESET#";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra20.dtsi1 #include <dt-bindings/clock/tegra20-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 compatible = "nvidia,tegra20";
10 interrupt-parent = <&lic>;
13 compatible = "nvidia,tegra20-host1x", "simple-bus";
19 reset-names = "host1x";
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
H A Dtegra30.dtsi1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra30-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&lic>;
13 pcie-controller@00003000 {
14 compatible = "nvidia,tegra30-pcie";
19 reg-names = "pads", "afi", "cs";
22 interrupt-names = "intr", "msi";
[all …]
H A Dtegra114.dtsi1 #include <dt-bindings/clock/tegra114-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra114-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&lic>;
14 compatible = "nvidia,tegra114-host1x", "simple-bus";
20 reset-names = "host1x";
22 #address-cells = <1>;
23 #size-cells = <1>;
[all …]
H A Dtegra210.dtsi1 #include <dt-bindings/clock/tegra210-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra210-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
10 interrupt-parent = <&lic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 pcie-controller@01003000 {
[all …]
H A Dtegra20-colibri.dts1 /dts-v1/;
3 #include "tegra20.dtsi"
7 compatible = "toradex,colibri_t20", "nvidia,tegra20";
10 stdout-path = &uarta;
19 usb1 = "/usb@c5004000"; /* On-module only, for ASIX */
28 display-timings {
31 clock-frequency = <25175000>;
34 hback-porch = <48>;
35 hfront-porch = <16>;
36 hsync-len = <96>;
[all …]
H A Dtegra124.dtsi1 #include <dt-bindings/clock/tegra124-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra124-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
14 interrupt-parent = <&lic>;
17 pcie-controller@01003000 {
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt1 NVIDIA Tegra20 Clock And Reset Controller
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : Should be "nvidia,tegra20-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
32 4 rtc
167 compatible = "nvidia,tegra20-car";
169 #clock-cells = <1>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Dwakeup-source.txt5 ----------------
7 "wakeup-source" boolean property.
18 ---------------------------------------------------------
20 1. "gpio-key,wakeup" Documentation/devicetree/bindings/input/gpio-keys{,-polled}.txt
21 2. "has-tpo" Documentation/devicetree/bindings/rtc/rtc-opal.txt
22 3. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt
25 4. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
26 5. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt
27 6. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
30 --------
[all …]
/openbmc/linux/drivers/rtc/
H A Drtc-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
3 * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
5 * Copyright (c) 2010-2019, NVIDIA Corporation.
18 #include <linux/rtc.h>
50 struct rtc_device *rtc; member
58 * RTC hardware is busy when it is updating its values over AHB once every
64 return readl(info->base + TEGRA_RTC_REG_BUSY) & 1; in tegra_rtc_check_busy()
70 * RTC to become busy with its periodic update, then returning once the RTC
84 * First wait for the RTC to become busy. This is when it posts its in tegra_rtc_wait_while_busy()
88 if (!retries--) in tegra_rtc_wait_while_busy()
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
[all …]

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