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/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-host1x.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra host1x controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The host1x top-level node defines a number of children, each
14 representing one of the host1x client modules defined in this binding.
19 - enum:
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt1 NVIDIA Tegra host1x
4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
8 in the host1x address space. Should be 1.
9 - #size-cells: The number of cells used to represent the size of an address
10 range in the host1x address space. Should be 1.
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
[all …]
/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dtegra20-dc.txt2 ------------------
5 U-Boot, and may change based on Linux activity)
12 - compatible : Should be "nvidia,tegra20-dc"
17 - nvidia,panel : phandle of LCD panel information
24 - nvidia,bits-per-pixel: number of bits per pixel (depth)
25 - nvidia,pwm : pwm to use to set display contrast (see tegra20-pwm.txt)
26 - nvidia,panel-timings: 4 cells containing required timings in ms:
28 * delay between panel_vdd-rise and data-rise
29 * delay between data-rise and backlight_vdd-rise
30 * delay between backlight_vdd and pwm-rise
[all …]
/openbmc/linux/drivers/gpu/host1x/
H A Ddev.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Tegra host1x driver
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
10 #include <linux/dma-mapping.h>
23 #include <trace/events/host1x.h>
27 #include <asm/dma-iommu.h>
45 void host1x_common_writel(struct host1x *host1x, u32 v, u32 r) in host1x_common_writel() argument
47 writel(v, host1x->common_regs + r); in host1x_common_writel()
50 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r) in host1x_hypervisor_writel() argument
52 writel(v, host1x->hv_regs + r); in host1x_hypervisor_writel()
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
12 compatible = "nvidia,tegra20";
13 interrupt-parent = <&lic>;
[all …]
H A Dtegra20-tec.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
8 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
10 host1x@50000000 {
20 interrupt-parent = <&gpio>;
23 gpio-controller;
24 #gpio-cells = <2>;
26 micdet-cfg = <0>;
27 micdet-delay = <100>;
[all …]
H A Dtegra20-plutux.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
8 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
10 host1x@50000000 {
20 interrupt-parent = <&gpio>;
23 gpio-controller;
24 #gpio-cells = <2>;
26 micdet-cfg = <0>;
27 micdet-delay = <100>;
[all …]
H A Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
[all …]
H A Dtegra20-medcom-wide.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
7 model = "Avionic Design Medcom-Wide board";
8 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
15 stdout-path = "serial0:115200n8";
18 host1x@50000000 {
35 interrupt-parent = <&gpio>;
38 gpio-controller;
39 #gpio-cells = <2>;
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddrm.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/host1x.h>
27 #include <asm/dma-iommu.h>
76 struct drm_device *drm = old_state->dev; in tegra_atomic_commit_tail()
77 struct tegra_drm *tegra = drm->dev_private; in tegra_atomic_commit_tail()
79 if (tegra->hub) { in tegra_atomic_commit_tail()
108 return -ENOMEM; in tegra_drm_open()
110 idr_init_base(&fpriv->legacy_contexts, 1); in tegra_drm_open()
111 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1); in tegra_drm_open()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra20.dtsi1 #include <dt-bindings/clock/tegra20-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 compatible = "nvidia,tegra20";
10 interrupt-parent = <&lic>;
12 host1x@50000000 {
13 compatible = "nvidia,tegra20-host1x", "simple-bus";
19 reset-names = "host1x";
21 #address-cells = <1>;
[all …]
H A Dtegra20-medcom-wide.dts1 /dts-v1/;
3 #include "tegra20-tamonten.dtsi"
6 model = "Avionic Design Medcom-Wide";
7 compatible = "ad,medcom-wide", "nvidia,tegra20";
10 stdout-path = &uartd;
22 host1x@50000000 {
36 clock-frequency = <216000000>;
51 left-margin = <2>;
52 right-margin = <47>;
53 hsync-len = <136>;
[all …]
H A Dtegra20-tec.dts1 /dts-v1/;
3 #include "tegra20-tamonten.dtsi"
7 compatible = "ad,tec", "nvidia,tegra20";
10 stdout-path = &uartd;
22 host1x@50000000 {
36 clock-frequency = <216000000>;
63 left-margin = <120>;
64 right-margin = <120>;
65 hsync-len = <16>;
66 lower-margin = <15>;
[all …]
H A Dtegra30.dtsi1 #include <dt-bindings/clock/tegra30-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra30-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&lic>;
13 pcie-controller@00003000 {
14 compatible = "nvidia,tegra30-pcie";
19 reg-names = "pads", "afi", "cs";
22 interrupt-names = "intr", "msi";
[all …]
H A Dtegra114.dtsi1 #include <dt-bindings/clock/tegra114-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra114-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&lic>;
13 host1x@50000000 {
14 compatible = "nvidia,tegra114-host1x", "simple-bus";
20 reset-names = "host1x";
22 #address-cells = <1>;
[all …]
H A Dtegra210.dtsi1 #include <dt-bindings/clock/tegra210-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra210-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
10 interrupt-parent = <&lic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 pcie-controller@01003000 {
[all …]
H A Dtegra20-colibri.dts1 /dts-v1/;
3 #include "tegra20.dtsi"
7 compatible = "toradex,colibri_t20", "nvidia,tegra20";
10 stdout-path = &uarta;
19 usb1 = "/usb@c5004000"; /* On-module only, for ASIX */
23 host1x@50000000 {
28 display-timings {
31 clock-frequency = <25175000>;
34 hback-porch = <48>;
35 hfront-porch = <16>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
[all …]
/openbmc/linux/drivers/staging/media/tegra-video/
H A Dvideo.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/host1x.h>
10 #include <media/v4l2-event.h>
21 tegra_channels_cleanup(vid->vi); in tegra_v4l2_dev_release()
24 media_device_unregister(&vid->media_dev); in tegra_v4l2_dev_release()
25 media_device_cleanup(&vid->media_dev); in tegra_v4l2_dev_release()
39 v4l2_event_queue(&chan->video, arg); in tegra_v4l2_dev_notify()
40 if (ev->type == V4L2_EVENT_SOURCE_CHANGE && vb2_is_streaming(&chan->queue)) in tegra_v4l2_dev_notify()
41 vb2_queue_error(&chan->queue); in tegra_v4l2_dev_notify()
51 return -ENOMEM; in host1x_video_probe()
[all …]
H A Dvi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/host1x.h>
16 #include <media/media-entity.h>
17 #include <media/v4l2-async.h>
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-dev.h>
21 #include <media/v4l2-subdev.h>
22 #include <media/videobuf2-v4l2.h>
44 * struct tegra_vi_ops - Tegra VI operations
[all …]
/openbmc/linux/drivers/gpu/host1x/hw/
H A Dhost1x01_hardware.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Tegra host1x Register Offsets for Tegra20 and Tegra30
5 * Copyright (c) 2010-2013 NVIDIA Corporation.
/openbmc/linux/Documentation/gpu/
H A Dtegra.rst6 the host1x controller. host1x supplies command streams, gathered from a push
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
15 The drm/tegra driver supports NVIDIA Tegra SoC generations since Tegra20. It
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
25 GPU and video engines via host1x.
30 The various host1x clients need to be bound together into a logical device in
32 this is implemented in the host1x driver. When a driver is registered with the
37 to the logical host1x device.
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt1 NVIDIA Tegra20 Clock And Reset Controller
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : Should be "nvidia,tegra20-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
56 28 host1x
167 compatible = "nvidia,tegra20-car";
169 #clock-cells = <1>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
[all …]

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