/openbmc/linux/Documentation/devicetree/bindings/gpio/ |
H A D | nvidia,tegra20-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210) 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 16 - enum: 17 - nvidia,tegra20-gpio 18 - nvidia,tegra30-gpio [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | tegra20.dtsi | 1 #include <dt-bindings/clock/tegra20-car.h> 2 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 compatible = "nvidia,tegra20"; 10 interrupt-parent = <&lic>; 13 compatible = "nvidia,tegra20-host1x", "simple-bus"; 19 reset-names = "host1x"; 21 #address-cells = <1>; 22 #size-cells = <1>; [all …]
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H A D | tegra30.dtsi | 1 #include <dt-bindings/clock/tegra30-car.h> 2 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/memory/tegra30-mc.h> 4 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 interrupt-parent = <&lic>; 13 pcie-controller@00003000 { 14 compatible = "nvidia,tegra30-pcie"; 19 reg-names = "pads", "afi", "cs"; 22 interrupt-names = "intr", "msi"; [all …]
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H A D | tegra114.dtsi | 1 #include <dt-bindings/clock/tegra114-car.h> 2 #include <dt-bindings/gpio/tegra-gpio.h> 3 #include <dt-bindings/memory/tegra114-mc.h> 4 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 interrupt-parent = <&lic>; 14 compatible = "nvidia,tegra114-host1x", "simple-bus"; 20 reset-names = "host1x"; 22 #address-cells = <1>; 23 #size-cells = <1>; [all …]
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H A D | tegra20-medcom-wide.dts | 1 /dts-v1/; 3 #include "tegra20-tamonten.dtsi" 6 model = "Avionic Design Medcom-Wide"; 7 compatible = "ad,medcom-wide", "nvidia,tegra20"; 10 stdout-path = &uartd; 36 clock-frequency = <216000000>; 51 left-margin = <2>; 52 right-margin = <47>; 53 hsync-len = <136>; 54 lower-margin = <21>; [all …]
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H A D | tegra20-tec.dts | 1 /dts-v1/; 3 #include "tegra20-tamonten.dtsi" 7 compatible = "ad,tec", "nvidia,tegra20"; 10 stdout-path = &uartd; 36 clock-frequency = <216000000>; 63 left-margin = <120>; 64 right-margin = <120>; 65 hsync-len = <16>; 66 lower-margin = <15>; 67 upper-margin = <15>; [all …]
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H A D | tegra20-trimslice.dts | 1 /dts-v1/; 3 #include "tegra20.dtsi" 7 compatible = "compulab,trimslice", "nvidia,tegra20"; 10 stdout-path = &uarta; 25 clock-frequency = <216000000>; 30 spi-max-frequency = <25000000>; 33 pcie-controller@80003000 { 36 avdd-pex-supply = <&pci_vdd_reg>; 37 vdd-pex-supply = <&pci_vdd_reg>; 38 avdd-pex-pll-supply = <&pci_vdd_reg>; [all …]
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/openbmc/u-boot/doc/device-tree-bindings/video/ |
H A D | tegra20-dc.txt | 2 ------------------ 5 U-Boot, and may change based on Linux activity) 12 - compatible : Should be "nvidia,tegra20-dc" 17 - nvidia,panel : phandle of LCD panel information 24 - nvidia,bits-per-pixel: number of bits per pixel (depth) 25 - nvidia,pwm : pwm to use to set display contrast (see tegra20-pwm.txt) 26 - nvidia,panel-timings: 4 cells containing required timings in ms: 28 * delay between panel_vdd-rise and data-rise 29 * delay between data-rise and backlight_vdd-rise 30 * delay between backlight_vdd and pwm-rise [all …]
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/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra20-acer-a500-picasso.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/atmel-maxtouch.h> 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/input/input.h> 7 #include <dt-bindings/thermal/thermal.h> 9 #include "tegra20.dtsi" 10 #include "tegra20-cpu-opp.dtsi" 11 #include "tegra20-cpu-opp-microvolt.dtsi" 15 compatible = "acer,picasso", "nvidia,tegra20"; [all …]
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H A D | tegra20.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra20-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra20-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/soc/tegra-pmc.h> 9 #include "tegra20-peripherals-opp.dtsi" 12 compatible = "nvidia,tegra20"; 13 interrupt-parent = <&lic>; [all …]
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H A D | tegra20-asus-tf101.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/atmel-maxtouch.h> 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/input/input.h> 7 #include <dt-bindings/thermal/thermal.h> 9 #include "tegra20.dtsi" 10 #include "tegra20-cpu-opp.dtsi" 11 #include "tegra20-cpu-opp-microvolt.dtsi" 15 compatible = "asus,tf101", "nvidia,tegra20"; [all …]
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H A D | tegra20-paz00.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 5 #include <dt-bindings/thermal/thermal.h> 7 #include "tegra20.dtsi" 8 #include "tegra20-cpu-opp.dtsi" 9 #include "tegra20-cpu-opp-microvolt.dtsi" 13 compatible = "compal,paz00", "nvidia,tegra20"; 25 stdout-path = "serial0:115200n8"; 44 vdd-supply = <&hdmi_vdd_reg>; [all …]
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H A D | tegra20-colibri.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include "tegra20.dtsi" 22 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 23 nvidia,hpd-gpio = 24 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 25 pll-supply = <®_1v8_avdd_hdmi_pll>; 26 vdd-supply = <®_3v3_avdd_hdmi>; 30 gpio@6000d000 { 31 lan-reset-n-hog { 32 gpio-hog; [all …]
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H A D | tegra20-tec.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra20-tamonten.dtsi" 8 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; 20 interrupt-parent = <&gpio>; 23 gpio-controller; 24 #gpio-cells = <2>; 26 micdet-cfg = <0>; 27 micdet-delay = <100>; 28 gpio-cfg = <0xffffffff [all …]
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H A D | tegra20-plutux.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra20-tamonten.dtsi" 8 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; 20 interrupt-parent = <&gpio>; 23 gpio-controller; 24 #gpio-cells = <2>; 26 micdet-cfg = <0>; 27 micdet-delay = <100>; 28 gpio-cfg = <0xffffffff [all …]
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H A D | tegra20-medcom-wide.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "tegra20-tamonten.dtsi" 7 model = "Avionic Design Medcom-Wide board"; 8 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; 15 stdout-path = "serial0:115200n8"; 35 interrupt-parent = <&gpio>; 38 gpio-controller; 39 #gpio-cells = <2>; 41 micdet-cfg = <0>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/tegra/ |
H A D | nvidia,tegra20-host1x.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 13 description: The host1x top-level node defines a number of children, each 19 - enum: 20 - nvidia,tegra20-host1x 21 - nvidia,tegra30-host1x [all …]
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H A D | nvidia,tegra20-dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^dc@[0-9a-f]+$" 19 - enum: 20 - nvidia,tegra20-dc 21 - nvidia,tegra30-dc [all …]
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H A D | nvidia,tegra20-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^hdmi@[0-9a-f]+$" 19 - enum: 20 - nvidia,tegra20-hdmi 21 - nvidia,tegra30-hdmi [all …]
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H A D | nvidia,tegra20-dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 16 - enum: 17 - nvidia,tegra20-dsi 18 - nvidia,tegra30-dsi 19 - nvidia,tegra114-dsi [all …]
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/openbmc/u-boot/doc/device-tree-bindings/gpu/ |
H A D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x" 5 - reg: Physical base address and length of the controller's registers. 6 - interrupts: The interrupt outputs from the controller. 7 - #address-cells: The number of cells used to represent physical base addresses 9 - #size-cells: The number of cells used to represent the size of an address 11 - ranges: The mapping of the host1x address space to the CPU address space. 12 - clocks: Must contain one entry, for the module clock. 13 See ../clocks/clock-bindings.txt for details. 14 - resets: Must contain an entry for each entry in reset-names. 16 - reset-names: Must include the following entries: [all …]
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/openbmc/u-boot/doc/device-tree-bindings/gpio/ |
H A D | nvidia,tegra20-gpio.txt | 1 NVIDIA Tegra GPIO controller 4 - compatible : "nvidia,tegra<chip>-gpio" 5 - reg : Physical base address and length of the controller's registers. 6 - interrupts : The interrupt outputs from the controller. For Tegra20, 9 - #gpio-cells : Should be two. The first cell is the pin number and the 11 - bit 0 specifies polarity (0 for normal, 1 for inverted) 12 - gpio-controller : Marks the device node as a GPIO controller. 13 - #interrupt-cells : Should be 2. 14 The first cell is the GPIO number. 17 1 = low-to-high edge triggered. [all …]
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | nvidia,tegra20-ac97.txt | 4 - compatible : "nvidia,tegra20-ac97" 5 - reg : Should contain AC97 controller registers location and length 6 - interrupts : Should contain AC97 interrupt 7 - resets : Must contain an entry for each entry in reset-names. 9 - reset-names : Must include the following entries: 10 - ac97 11 - dmas : Must contain an entry for each entry in clock-names. 13 - dma-names : Must include the following entries: 14 - rx 15 - tx [all …]
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/openbmc/u-boot/doc/device-tree-bindings/usb/ |
H A D | tegra-usb.txt | 9 - compatible : Should be "nvidia,tegra20-ehci" for USB controllers 11 - phy_type : Should be one of "ulpi" or "utmi". 12 - nvidia,vbus-gpio : If present, specifies a gpio that needs to be 16 - dr_mode : dual role mode. Indicates the working mode for 17 nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral", 22 - nvidia,has-legacy-mode : boolean indicates whether this controller can
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/openbmc/linux/Documentation/devicetree/bindings/mmc/ |
H A D | nvidia,tegra20-sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 18 mmc-controller.yaml and the properties for the Tegra SDHCI controller. 23 - enum: 24 - nvidia,tegra20-sdhci 25 - nvidia,tegra30-sdhci [all …]
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