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/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra186.dtsi2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/power/tegra186-powergate.h>
7 #include <dt-bindings/reset/tegra186-reset.h>
10 compatible = "nvidia,tegra186";
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
[all …]
H A Dtegra186-p2771-0000.dtsi1 #include "tegra186.dtsi"
4 model = "NVIDIA P2771-0000";
5 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
8 stdout-path = &uarta;
14 i2c0 = "/bpmp/i2c";
30 phy-reset-gpios = <&gpio_main TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
51 wp-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
52 bus-width = <4>;
57 bus-width = <8>;
58 non-removable;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The BPMP is a specific processor in Tegra chip, which is designed for
17 defines the resources that would be used by the BPMP firmware driver,
19 CPU and BPMP.
[all …]
/openbmc/u-boot/doc/device-tree-bindings/firmware/
H A Dnvidia,tegra186-bpmp.txt1 NVIDIA Tegra Boot and Power Management Processor (BPMP)
3 The BPMP is a specific processor in Tegra chip, which is designed for
6 defines the resources that would be used by the BPMP firmware driver,
8 and BPMP.
11 - name : Should be bpmp
12 - compatible
15 - "nvidia,tegra186-bpmp"
16 - mboxes : The phandle of mailbox controller and the mailbox specifier.
17 - shmem : List of the phandle of the TX and RX shared memory area that
18 the IPC between CPU and BPMP is based on.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra186-display.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) Display Hub
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
[all …]
H A Dnvidia,tegra20-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
[all …]
H A Dnvidia,tegra186-dsi-padctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dsi-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^padctl@[0-9a-f]+$"
18 const: nvidia,tegra186-dsi-padctl
25 - description: module reset
27 reset-names:
[all …]
/openbmc/u-boot/doc/device-tree-bindings/i2c/
H A Dnvidia,tegra186-bpmp-i2c.txt1 NVIDIA Tegra186 BPMP I2C controller
3 In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
5 running on other CPUs must perform IPC to the BPMP in order to execute
9 The BPMP I2C node must be located directly inside the main BPMP node. See
10 ../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
16 - compatible:
19 - "nvidia,tegra186-bpmp-i2c".
20 - #address-cells: Address cells for I2C device address.
21 Single-cell integer.
23 - #size-cells:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dnvidia,tegra186-bpmp-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) BPMP I2C controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 In Tegra186 and later, the BPMP (Boot and Power Management Processor)
17 the BPMP in order to execute transactions on that I2C bus. This
20 The BPMP I2C node must be located directly inside the main BPMP node.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dnvidia,tegra186-bpmp-thermal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) BPMP thermal sensor
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 In Tegra186, the BPMP (Boot and Power Management Processor) implements
17 sensor that is exposed by BPMP.
19 The BPMP thermal node must be located directly inside the main BPMP
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra186-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 xHCI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 const: nvidia,tegra186-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
[all …]
/openbmc/linux/drivers/firmware/tegra/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 tegra-bpmp-y = bpmp.o
3 tegra-bpmp-$(CONFIG_ARCH_TEGRA_210_SOC) += bpmp-tegra210.o
4 tegra-bpmp-$(CONFIG_ARCH_TEGRA_186_SOC) += bpmp-tegra186.o
5 tegra-bpmp-$(CONFIG_ARCH_TEGRA_194_SOC) += bpmp-tegra186.o
6 tegra-bpmp-$(CONFIG_ARCH_TEGRA_234_SOC) += bpmp-tegra186.o
7 tegra-bpmp-$(CONFIG_DEBUG_FS) += bpmp-debugfs.o
8 obj-$(CONFIG_TEGRA_BPMP) += tegra-bpmp.o
9 obj-$(CONFIG_TEGRA_IVC) += ivc.o
/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Dnvidia,tegra186-ccplex-cluster.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/nvidia,tegra186-ccplex-cluster.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 CCPLEX Cluster
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra186-ccplex-cluster
20 nvidia,bpmp:
21 description: phandle to the BPMP used to query CPU frequency tables
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra186-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
27 pattern: "^memory-controller@[0-9a-f]+$"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/gpu/host1x/
H A Dnvidia,tegra210-nvjpg.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvjpg@[0-9a-f]*$"
24 - nvidia,tegra210-nvjpg
25 - nvidia,tegra186-nvjpg
26 - nvidia,tegra194-nvjpg
[all …]
H A Dnvidia,tegra210-nvenc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
[all …]
H A Dnvidia,tegra210-nvdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra210-nvdec
25 - nvidia,tegra186-nvdec
26 - nvidia,tegra194-nvdec
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra186-dspk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra186 DSPK Controller
11 Density Modulation (PDM) transmitter that up-samples the input to
13 over sampled Pulse Code Modulation (PCM) input to the desired 1-bit
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
21 - $ref: dai-common.yaml#
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dtegra186-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
12 #include <soc/tegra/bpmp.h>
13 #include <soc/tegra/bpmp-abi.h>
28 /* CPU0 - A57 Cluster */
33 /* CPU1 - Denver Cluster */
38 /* CPU2 - Denver Cluster */
43 /* CPU3 - A57 Cluster */
48 /* CPU4 - A57 Cluster */
53 /* CPU5 - A57 Cluster */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
[all …]
H A Dnvidia,tegra-ccplex-cluster.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
11 - Mikko Perttunen <mperttunen@nvidia.com>
12 - Jon Hunter <jonathanh@nvidia.com>
13 - Thierry Reding <thierry.reding@gmail.com>
16 The Tegra CPU COMPLEX CLUSTER area contains memory-mapped
21 pattern: "ccplex@([0-9a-f]+)$"
[all …]
/openbmc/linux/drivers/memory/tegra/
H A Dtegra186-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <soc/tegra/bpmp.h>
22 struct tegra_bpmp *bpmp; member
42 * to control the EMC frequency. The top-level directory can be found here:
48 * - available_rates: This file contains a list of valid, space-separated
51 * - min_rate: Writing a value to this file sets the given frequency as the
56 * - max_rate: Similarily to the min_rate file, writing a value to this file
68 for (i = 0; i < emc->num_dvfs; i++) in tegra186_emc_validate_rate()
69 if (rate == emc->dvfs[i].rate) in tegra186_emc_validate_rate()
78 struct tegra186_emc *emc = s->private; in tegra186_emc_debug_available_rates_show()
[all …]
/openbmc/u-boot/drivers/clk/tegra/
H A DKconfig2 bool "Enable Tegra CAR-based clock driver"
5 Enable support for manipulating Tegra's on-SoC clocks via direct
9 bool "Enable Tegra186 BPMP-based clock driver"
12 Enable support for manipulating Tegra's on-SoC clocks via IPC
13 requests to the BPMP (Boot and Power Management Processor).

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