| /openbmc/linux/drivers/cpufreq/ |
| H A D | sa1110-cpufreq.c | 37 u_char trcd; /* activate to r/w (ns) */ member
54 .trcd = 20,
63 .trcd = 20,
72 .trcd = 27,
89 .trcd = 24, /* 3 CLKs */
98 .trcd = 20,
107 .trcd = 20,
186 ns_to_cycles(sdram->trcd, mem_khz)); in sdram_calculate_timing()
353 printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d" in sa1110_clk_init()
355 sdram->tck, sdram->trcd, sdram->trp, in sa1110_clk_init()
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| /openbmc/linux/drivers/memory/ |
| H A D | jedec_ddr_data.c | 38 .tRCD = 18000,
59 .tRCD = 18000,
80 .tRCD = 18000,
101 .tRCD = 18000,
122 .tRCD = 3,
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| H A D | of_memory.c | 39 ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); in of_get_min_tck()
71 ret |= of_property_read_u32(np, "tRCD", &tim->tRCD); in of_do_get_timings()
179 ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); in of_lpddr3_get_min_tck()
225 ret |= of_property_read_u32(np, "tRCD", &tim->tRCD); in of_lpddr3_do_get_timings()
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| H A D | jedec_ddr.h | 151 u32 tRCD; member
175 u32 tRCD; member
232 u32 tRCD; member
261 u32 tRCD; member
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | elpida_ecb240abacn.dtsi | 13 tRCD-min-tck = <3>;
29 tRCD = <18000>;
51 tRCD = <18000>;
|
| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | emif.c | 27 .tRCD = 18,
51 .tRCD = 18,
80 .tRCD = 3,
|
| H A D | sdram_elpida.c | 194 .tRCD = 18,
217 .tRCD = 18,
240 .tRCD = 18,
262 .tRCD = 3,
|
| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2.yaml | 91 tRCD-min-tck:
152 tRCD-min-tck = <3>;
168 tRCD = <18000>;
189 tRCD = <18000>;
|
| H A D | jedec,lpddr3.yaml | 93 tRCD-min-tck:
206 tRCD-min-tck = <3>;
231 tRCD = <10000>;
|
| H A D | jedec,lpddr2-timings.yaml | 57 tRCD:
126 tRCD = <18000>;
|
| H A D | jedec,lpddr3-timings.yaml | 69 tRCD:
145 tRCD = <10000>;
|
| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-dmc.txt | 50 rockchip,trcd: tRCD,AC timing parameters from the memory data-sheet
68 trcd
142 rockchip,trcd = <10>;
|
| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | emif.c | 28 .tRCD = 18,
57 .tRCD = 3,
|
| /openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 13 u8 trcd = ns_to_t(20); in mctl_set_timing_params() local
64 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
|
| H A D | lpddr3_stock.c | 13 u8 trcd = max(ns_to_t(24), 2); in mctl_set_timing_params() local
63 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
|
| H A D | ddr3_1333.c | 13 u8 trcd = ns_to_t(15); in mctl_set_timing_params() local
67 writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | in mctl_set_timing_params()
|
| /openbmc/u-boot/board/freescale/mx6memcal/ |
| H A D | spl.c | 253 .trcd = 1375,
267 .trcd = 1375,
281 .trcd = 1375,
295 .trcd = 1350,
|
| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | lc_common_dimm_params.c | 475 * which comes from Trcd, and also note that: in compute_lowest_common_dimm_parameters()
510 * tRCD, i.e. the READ or WRITE command is in the cycle in compute_lowest_common_dimm_parameters()
518 * Validation: AL is less than tRCD, and within the other in compute_lowest_common_dimm_parameters()
541 * AL <= tRCD(min) in compute_lowest_common_dimm_parameters()
544 printf("Error: invalid additive latency exceeds tRCD(min).\n"); in compute_lowest_common_dimm_parameters()
|
| /openbmc/u-boot/include/ |
| H A D | spd.h | 44 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ member
|
| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_rk3036.h | 55 u32 trcd; member
252 u32 trcd; member
|
| /openbmc/u-boot/drivers/ddr/altera/ |
| H A D | sdram_s10.c | 267 * RDTOMISS = tRTP + tRP + tRCD - BL/2 in sdram_mmr_init_full()
268 * WRTOMISS = WL + tWR + tRP + tRCD and in sdram_mmr_init_full()
272 * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD in sdram_mmr_init_full()
|
| /openbmc/u-boot/drivers/ram/ |
| H A D | stm32_sdram.c | 126 u8 trcd; member
196 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
206 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT in stm32_sdram_init()
|
| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | opos6ul.c | 205 .trcd = 1500,
246 mem_ddr.trcd = 1375; in spl_dram_init()
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| /openbmc/u-boot/doc/device-tree-bindings/memory-controllers/ |
| H A D | st,stm32-fmc.txt | 24 trcd
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| /openbmc/u-boot/board/liebherr/mccmon6/ |
| H A D | spl.c | 139 .trcd = 1375,
153 .trcd = 1350,
|