| /openbmc/linux/drivers/memory/ |
| H A D | jedec_ddr_data.c | 45 .tCKESR = 15000,
66 .tCKESR = 15000,
87 .tCKESR = 15000,
108 .tCKESR = 15000,
130 .tCKESR = 3,
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| H A D | of_memory.c | 47 ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR); in of_get_min_tck()
78 ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR); in of_do_get_timings()
194 ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR); in of_lpddr3_get_min_tck()
237 ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR); in of_lpddr3_do_get_timings()
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| H A D | jedec_ddr.h | 158 u32 tCKESR; member
183 u32 tCKESR; member
247 u32 tCKESR; member
276 u32 tCKESR; member
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | elpida_ecb240abacn.dtsi | 21 tCKESR-min-tck = <3>;
36 tCKESR = <15000>;
58 tCKESR = <15000>;
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| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | emif.c | 37 .tCKESR = 15,
61 .tCKESR = 15,
88 .tCKESR = 3,
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| H A D | sdram_elpida.c | 204 .tCKESR = 15,
227 .tCKESR = 15,
250 .tCKESR = 15,
270 .tCKESR = 3,
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2.yaml | 112 tCKESR-min-tck:
160 tCKESR-min-tck = <3>;
175 tCKESR = <15000>;
196 tCKESR = <15000>;
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| H A D | jedec,lpddr3.yaml | 48 tCKESR-min-tck:
199 tCKESR-min-tck = <2>;
225 tCKESR = <3750>;
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| H A D | jedec,lpddr2-timings.yaml | 26 tCKESR:
120 tCKESR = <15000>;
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| H A D | jedec,lpddr3-timings.yaml | 38 tCKESR:
139 tCKESR = <3750>;
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| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | emif.c | 38 .tCKESR = 15,
65 .tCKESR = 3,
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| H A D | sdram.c | 626 .tCKESR = 15,
646 .tCKESR = 3,
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| /openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 30 u8 tckesr = 4; in mctl_set_timing_params() local
67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 30 u8 tckesr = 5; in mctl_set_timing_params() local
66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| H A D | ddr3_1333.c | 30 u8 tckesr = 4; in mctl_set_timing_params() local
70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_rk3036.h | 73 u32 tckesr; member
270 u32 tckesr; member
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| H A D | sdram.h | 76 u32 tckesr; member
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| H A D | ddr_rk3368.h | 77 u32 tckesr; member
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| H A D | sdram_rk322x.h | 109 u32 tckesr; member
235 u32 tckesr; member
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| /openbmc/u-boot/arch/arm/include/asm/arch-vf610/ |
| H A D | ddrmc-vf610.h | 31 u8 tckesr; member
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a83t.c | 114 u8 tckesr = 4; in auto_set_timing_para() local
158 tckesr = 5; in auto_set_timing_para()
180 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
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| H A D | dram_sun8i_a33.c | 114 u8 tckesr = 4; in auto_set_timing_para() local
148 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
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| H A D | dram_sun9i.c | 144 /* struct dram_sun9i_timing tCKESR; */
412 * self-refresh timings (keep below power-down timings, as tCKESR in mctl_channel_init()
419 const u32 tCKESR = tCKE + 1; in mctl_channel_init() local
552 (MCTL_DIV2(tCKESR) << 8) | (MCTL_DIV2(tCKE) << 0), in mctl_channel_init()
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| /openbmc/u-boot/board/phytec/pcm052/ |
| H A D | pcm052.c | 227 .tckesr = 4, in dram_init()
282 .tckesr = 4, in dram_init()
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-dmc.txt | 86 tckesr
|