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/openbmc/linux/arch/openrisc/kernel/
H A Dsync-timer.c6 * All CPUs will have their count registers synchronised to the CPU0 next time
42 * then the last pass is more or less synchronised and in synchronise_count_master()
/openbmc/linux/arch/mips/kernel/
H A Dsync-r4k.c5 * All CPUs will have their count registers synchronised to the CPU0 next time
39 * then the last pass is more or less synchronised and in synchronise_count_master()
H A Dsmp.c383 /* The CPU is running and counters synchronised, now mark it online */ in start_secondary()
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-flash.rst34 Synchronised LED flash (hardware strobe)
37 The synchronised LED flash is pre-programmed by the host (power and
H A Dmetafmt-d4xx.rst132 - Byte 0: bit 0: depth and RGB are synchronised, bit 1: external trigger
/openbmc/linux/Documentation/arch/arm/samsung/
H A Dgpio.rst19 GPIO numbering is synchronised between the Samsung and gpiolib system.
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_syncmap.c146 * If we have already synchronised this @root timeline with another (@id) then
151 * Returns true if the two timelines are already synchronised wrt to @seqno,
343 * @id: the context id (other timeline) we have synchronised to
/openbmc/linux/arch/arm/mach-omap2/
H A Domap4-common.c71 * accesses) are properly synchronised with writes to DMA coherent memory
78 * Note: the SRAM path is not synchronised via mb() and wmb().
/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dmicrochip,corepwm.yaml47 synchronised mode for all channels it has been synthesised for.
/openbmc/linux/arch/arm64/kvm/hyp/nvhe/
H A Ddebug-sr.c47 /* The host page table is installed, but not yet synchronised */ in __debug_restore_spe()
/openbmc/linux/include/linux/
H A Ddm-dirty-log.h98 * tells you if an area is synchronised, the other
/openbmc/linux/drivers/mailbox/
H A Dplatform_mhu.c5 * Synchronised with arm_mhu.c from :
/openbmc/openbmc/meta-openembedded/meta-gnome/recipes-gnome/gnome-disk-utility/gnome-disk-utility/
H A D0001-gnome-disk-utility-remove-libcanberra-dependency.patch28 # Keep the version here synchronised with subprojects/libhandy.wrap
/openbmc/linux/rust/kernel/
H A Dtask.rs75 // synchronised by C code (e.g., `signal_pending`).
/openbmc/linux/tools/include/uapi/linux/
H A Dstat.h83 * - the datum will be synchronised to the server if AT_STATX_FORCE_SYNC is
/openbmc/linux/include/uapi/linux/
H A Dstat.h83 * - the datum will be synchronised to the server if AT_STATX_FORCE_SYNC is
/openbmc/linux/arch/parisc/kernel/
H A Dtime.c56 * an Interval Timer of its own and they are not synchronised.
/openbmc/linux/drivers/mfd/
H A Ducb1x00-core.c228 * synchronised ADC conversions (via the ADCSYNC pin) must wait
234 * If called for a synchronised ADC conversion, it may sleep
/openbmc/linux/Documentation/networking/
H A Dipvs-sysctl.rst298 0: All types of connections are synchronised
/openbmc/linux/arch/sh/mm/
H A Dfault.c156 * The page tables are fully synchronised so there must in vmalloc_sync_one()
/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dsubcore.c109 * subcores have separate timebases SPRs but these are pre-synchronised by
/openbmc/linux/sound/soc/
H A Dsoc-jack.c29 * synchronised.
/openbmc/qemu/docs/devel/
H A Dmulti-thread-tcg.rst191 time in a synchronised manner.
/openbmc/linux/drivers/iio/adc/
H A Dnau7802.c161 * Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT
/openbmc/linux/arch/arm/include/asm/
H A Dcacheflush.h265 * Harvard caches are synchronised for the user space address range.

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