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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dadi,max77857.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Analog Devices MAX77857 Buck-Boost Converter
11 - Ibrahim Tilki <Ibrahim.Tilki@analog.com>
12 - Okan Sahin <Okan.Sahin@analog.com>
14 description: Analog Devices MAX77857 Buck-Boost Converter
19 - adi,max77831
20 - adi,max77857
21 - adi,max77859
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H A Dqcom,rpm-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/qcom,rpm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 The regulator node houses sub-nodes for each regulator within the device.
16 Each sub-node is identified using the node's name, with valid values listed
28 l29, lvs1, lvs2, lvs3, lvs4, lvs5, lvs6, lvs7, usb-switch, hdmi-switch,
37 - Bjorn Andersson <andersson@kernel.org>
42 - qcom,rpm-pm8058-regulators
43 - qcom,rpm-pm8901-regulators
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H A Dmps,mp886x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jisheng Zhang <jszhang@kernel.org>
13 - $ref: regulator.yaml#
18 - mps,mp8867
19 - mps,mp8869
24 enable-gpios:
28 mps,fb-voltage-divider:
31 $ref: /schemas/types.yaml#/definitions/uint32-array
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/openbmc/linux/sound/soc/codecs/
H A Dtda7419.c1 // SPDX-License-Identifier: GPL-2.0-only
136 if (tvc->reg == tvc->rreg) in tda7419_vol_is_stereo()
146 (struct tda7419_vol_control *)kcontrol->private_value; in tda7419_vol_info()
148 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in tda7419_vol_info()
149 uinfo->count = tda7419_vol_is_stereo(tvc) ? 2 : 1; in tda7419_vol_info()
150 uinfo->value.integer.min = tvc->min; in tda7419_vol_info()
151 uinfo->value.integer.max = tvc->max; in tda7419_vol_info()
163 val = 0 - val; in tda7419_vol_get_value()
166 val = val - thresh; in tda7419_vol_get_value()
168 val = thresh - val; in tda7419_vol_get_value()
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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2012
29 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
30 writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); in clock_init_safe()
36 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
38 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); in clock_init_safe()
40 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
42 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
43 setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); in clock_init_safe()
57 &ccm->apb1_clk_div_cfg); in clock_init_uart()
[all …]
/openbmc/linux/init/
H A Dcalibrate.c1 // SPDX-License-Identifier: GPL-2.0
29 * Also, this code tries to handle non-maskable asynchronous events
32 #define DELAY_CALIBRATION_TICKS ((HZ < 100) ? 1 : (HZ/100))
44 int max = -1; /* index of measured_times with max/min values or not set */ in calibrate_delay_direct()
45 int min = -1; in calibrate_delay_direct()
55 * will not do. As we don't really know whether jiffy switch in calibrate_delay_direct()
60 * 1. pre_start <- When we are sure that jiffy switch hasn't happened in calibrate_delay_direct()
61 * 2. check jiffy switch in calibrate_delay_direct()
62 * 3. start <- timer value before or after jiffy switch in calibrate_delay_direct()
63 * 4. post_start <- When we are sure that jiffy switch has happened in calibrate_delay_direct()
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/openbmc/linux/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
34 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
37 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
40 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
[all …]
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3128-cru.h>
29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
44 /* All PLLs have same VCO and output frequency range restrictions. */ in rkclk_set_pll()
45 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
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H A Dclk_rk3399.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3399-cru.h>
41 ((input_rate) / (output_rate) - 1);
44 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
46 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
234 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
238 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
306 * FOUTVCO = Fractional PLL non-divided output frequency
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H A Dclk_rk3188.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
10 #include <dt-structs.h>
19 #include <dt-bindings/clock/rk3188-cru.h>
20 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
73 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
74 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
75 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
76 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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H A Dclk_rk3328.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
18 #include <dt-bindings/clock/rk3328-cru.h>
29 ((input_rate) / (output_rate) - 1);
32 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
34 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
198 * FOUTVCO = Fractional PLL non-divided output frequency
199 * FOUTPOSTDIV = Fractional PLL divided output frequency
201 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
214 switch (clk_id) { in rkclk_set_pll()
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H A Dclk_rk3288.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
133 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
134 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
135 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
136 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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/openbmc/u-boot/drivers/sound/
H A Dwm8994.c1 // SPDX-License-Identifier: GPL-2.0+
31 int in; /* Input frequency in Hz */
32 int out; /* output frequency in Hz */
39 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
40 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
41 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
84 return dm_i2c_write(priv->dev, reg, val, 2); in wm8994_i2c_write()
94 * @return int value 0 for success, -1 in case of error.
102 ret = dm_i2c_read(priv->dev, reg, val, 1); in wm8994_i2c_read()
106 return -1; in wm8994_i2c_read()
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/openbmc/linux/drivers/iio/pressure/
H A Dzpa2326.c1 // SPDX-License-Identifier: GPL-2.0-only
34 * - get device out of low power mode,
35 * - setup hardware sampling period,
36 * - at end of period, upon data ready interrupt: pop pressure samples out of
38 * - when no longer needed, stop sampling process by putting device into
44 * Note that hardware sampling frequency is taken into account only when
70 /* 200 ms should be enough for the longest conversion time in one-shot mode. */
71 #define ZPA2326_CONVERSION_JIFFIES (HZ / 5)
78 * struct zpa2326_frequency - Hardware sampling frequency descriptor
79 * @hz : Frequency in Hertz.
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/openbmc/linux/include/linux/
H A Dtimex.h28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
58 #define ADJ_ADJTIME 0x8000 /* switch between adjtime/adjtimex modes */
59 #define ADJ_OFFSET_SINGLESHOT 0x0001 /* old-fashioned adjtime */
60 #define ADJ_OFFSET_READONLY 0x2000 /* read-only adjtime */
73 * when an interrupt takes places versus a high speed, fine-grained
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/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dspeed.c1 // SPDX-License-Identifier: GPL-2.0+
7 * (C) Copyright 2000-2002
24 volatile ccsr_gur_t *gur = &immap->im_gur; in get_sys_info()
27 plat_ratio = (gur->porpllsr) & 0x0000003e; in get_sys_info()
30 switch (plat_ratio) { in get_sys_info()
32 sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ; in get_sys_info()
44 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; in get_sys_info()
47 sys_info->freq_systembus = 0; in get_sys_info()
51 e600_ratio = (gur->porpllsr) & 0x003f0000; in get_sys_info()
54 switch (e600_ratio) { in get_sys_info()
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/openbmc/linux/drivers/clk/hisilicon/
H A Dclk-hi6220-stub.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
33 /* CPU dynamic frequency scaling */
71 regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq); in hi6220_acpu_get_freq()
80 /* set the frequency in sram */ in hi6220_acpu_set_freq()
81 regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq); in hi6220_acpu_set_freq()
89 mbox_send_message(stub_clk->mbox, &data); in hi6220_acpu_set_freq()
99 /* check the constrained frequency */ in hi6220_acpu_round_freq()
100 regmap_read(stub_clk->dfs_map, ACPU_DFS_FLAG, &limit_flag); in hi6220_acpu_round_freq()
102 regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, &limit_freq); in hi6220_acpu_round_freq()
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/openbmc/linux/sound/pci/hda/
H A Dhda_beep.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Digital Beep Input Interface for HD-audio codec
18 DIGBEEP_HZ_STEP = 46875, /* 46.875 Hz */
19 DIGBEEP_HZ_MIN = 93750, /* 93.750 Hz */
26 struct hda_codec *codec = beep->codec; in generate_tone()
28 if (tone && !beep->playing) { in generate_tone()
30 if (beep->power_hook) in generate_tone()
31 beep->power_hook(beep, true); in generate_tone()
32 beep->playing = 1; in generate_tone()
34 snd_hda_codec_write(codec, beep->nid, 0, in generate_tone()
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/openbmc/linux/include/linux/soundwire/
H A Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
75 * enum sdw_slave_status - Slave status
93 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
94 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
104 * enum sdw_command_response - Command response as defined by SDW spec
190 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
201 * enum sdw_dpn_type - Data port types
216 * enum sdw_clk_stop_mode - Clock Stop modes
219 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
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/openbmc/u-boot/drivers/clk/sifive/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
27 * pre-determined set of performance points.
30 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
31 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
39 #include "analogbits-wrpll-cln28hpc.h"
41 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
44 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
47 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
50 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
53 /* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */
[all …]
/openbmc/linux/include/media/
H A Dtuner-types.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum param_type - type of the tuner pameters
27 * struct tuner_range - define the frequencies supported by the tuner
29 * @limit: Max frequency supported by that range, in 62.5 kHz
30 * (TV) or 62.5 Hz (Radio), as defined by
32 * @config: Value of the band switch byte (BB) to setup this mode.
43 * #) band switch byte (BB)
54 * struct tuner_params - Parameters to be used to setup the tuner. Those
55 * are used by drivers/media/tuners/tuner-types.c in
57 * the parameters are for tuners based on tda9887 IF-PLL
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/openbmc/linux/Documentation/admin-guide/media/
H A Dvivid.rst1 .. SPDX-License-Identifier: GPL-2.0
13 Each input can be a webcam, TV capture device, S-Video capture device or an HDMI
14 capture device. Each output can be an S-Video output device or an HDMI output
23 - Support for read()/write(), MMAP, USERPTR and DMABUF streaming I/O.
24 - A large list of test patterns and variations thereof
25 - Working brightness, contrast, saturation and hue controls
26 - Support for the alpha color component
27 - Full colorspace support, including limited/full RGB range
28 - All possible control types are present
29 - Support for various pixel aspect ratios and video aspect ratios
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/openbmc/qemu/hw/watchdog/
H A Dsbsa_gwdt.c14 * option) any later version. See the COPYING file in the top-level directory.
21 #include "hw/qdev-properties.h"
29 .name = "sbsa-gwdt",
53 switch (addr) { in sbsa_gwdt_rread()
59 ret = s->id; in sbsa_gwdt_rread()
73 switch (addr) { in sbsa_gwdt_read()
75 ret = s->wcs; in sbsa_gwdt_read()
78 ret = s->worl; in sbsa_gwdt_read()
81 ret = s->woru; in sbsa_gwdt_read()
84 ret = s->wcvl; in sbsa_gwdt_read()
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/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-davinci.txt7 - compatible: "ti,davinci-i2c" or "ti,keystone-i2c";
8 - reg : Offset and length of the register set for the device
9 - clocks: I2C functional clock phandle.
11 Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
13 SoC-specific Required Properties:
17 - power-domains: Should contain a phandle to a PM domain provider node
20 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
23 - interrupts : standard interrupt property.
24 - clock-frequency : desired I2C bus clock frequency in Hz.
25 - ti,has-pfunc: boolean; if defined, it indicates that SoC supports PFUNC
[all …]
H A Dnuvoton,npcm7xx-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 slave mode. Each controller can switch between master and slave at run time
15 - Tali Perry <tali.perry1@gmail.com>
20 - nuvoton,npcm750-i2c
21 - nuvoton,npcm845-i2c
33 clock-frequency:
34 description: Desired I2C bus clock frequency in Hz. If not specified,
[all …]

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