1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2a47a12beSStefan Roese /* 3a47a12beSStefan Roese * Copyright 2004 Freescale Semiconductor. 4a47a12beSStefan Roese * Jeff Brown 5a47a12beSStefan Roese * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 6a47a12beSStefan Roese * 7a47a12beSStefan Roese * (C) Copyright 2000-2002 8a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 9a47a12beSStefan Roese */ 10a47a12beSStefan Roese 11a47a12beSStefan Roese #include <common.h> 12a47a12beSStefan Roese #include <mpc86xx.h> 13a47a12beSStefan Roese #include <asm/processor.h> 14a47a12beSStefan Roese #include <asm/io.h> 15a47a12beSStefan Roese 16a47a12beSStefan Roese DECLARE_GLOBAL_DATA_PTR; 17a47a12beSStefan Roese 18a47a12beSStefan Roese /* used in some defintiions of CONFIG_SYS_CLK_FREQ */ 19a47a12beSStefan Roese extern unsigned long get_board_sys_clk(unsigned long dummy); 20a47a12beSStefan Roese get_sys_info(sys_info_t * sys_info)21997399faSPrabhakar Kushwahavoid get_sys_info(sys_info_t *sys_info) 22a47a12beSStefan Roese { 23a47a12beSStefan Roese volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 24a47a12beSStefan Roese volatile ccsr_gur_t *gur = &immap->im_gur; 25a47a12beSStefan Roese uint plat_ratio, e600_ratio; 26a47a12beSStefan Roese 27a47a12beSStefan Roese plat_ratio = (gur->porpllsr) & 0x0000003e; 28a47a12beSStefan Roese plat_ratio >>= 1; 29a47a12beSStefan Roese 30a47a12beSStefan Roese switch (plat_ratio) { 31a47a12beSStefan Roese case 0x0: 32997399faSPrabhakar Kushwaha sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ; 33a47a12beSStefan Roese break; 34a47a12beSStefan Roese case 0x02: 35a47a12beSStefan Roese case 0x03: 36a47a12beSStefan Roese case 0x04: 37a47a12beSStefan Roese case 0x05: 38a47a12beSStefan Roese case 0x06: 39a47a12beSStefan Roese case 0x08: 40a47a12beSStefan Roese case 0x09: 41a47a12beSStefan Roese case 0x0a: 42a47a12beSStefan Roese case 0x0c: 43a47a12beSStefan Roese case 0x10: 44997399faSPrabhakar Kushwaha sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; 45a47a12beSStefan Roese break; 46a47a12beSStefan Roese default: 47997399faSPrabhakar Kushwaha sys_info->freq_systembus = 0; 48a47a12beSStefan Roese break; 49a47a12beSStefan Roese } 50a47a12beSStefan Roese 51a47a12beSStefan Roese e600_ratio = (gur->porpllsr) & 0x003f0000; 52a47a12beSStefan Roese e600_ratio >>= 16; 53a47a12beSStefan Roese 54a47a12beSStefan Roese switch (e600_ratio) { 55a47a12beSStefan Roese case 0x10: 56997399faSPrabhakar Kushwaha sys_info->freq_processor = 2 * sys_info->freq_systembus; 57a47a12beSStefan Roese break; 58a47a12beSStefan Roese case 0x19: 59997399faSPrabhakar Kushwaha sys_info->freq_processor = 5 * sys_info->freq_systembus / 2; 60a47a12beSStefan Roese break; 61a47a12beSStefan Roese case 0x20: 62997399faSPrabhakar Kushwaha sys_info->freq_processor = 3 * sys_info->freq_systembus; 63a47a12beSStefan Roese break; 64a47a12beSStefan Roese case 0x39: 65997399faSPrabhakar Kushwaha sys_info->freq_processor = 7 * sys_info->freq_systembus / 2; 66a47a12beSStefan Roese break; 67a47a12beSStefan Roese case 0x28: 68997399faSPrabhakar Kushwaha sys_info->freq_processor = 4 * sys_info->freq_systembus; 69a47a12beSStefan Roese break; 70a47a12beSStefan Roese case 0x1d: 71997399faSPrabhakar Kushwaha sys_info->freq_processor = 9 * sys_info->freq_systembus / 2; 72a47a12beSStefan Roese break; 73a47a12beSStefan Roese default: 74997399faSPrabhakar Kushwaha sys_info->freq_processor = e600_ratio + 75997399faSPrabhakar Kushwaha sys_info->freq_systembus; 76a47a12beSStefan Roese break; 77a47a12beSStefan Roese } 78a47a12beSStefan Roese 79add63f94SPrabhakar Kushwaha sys_info->freq_localbus = sys_info->freq_systembus; 80a47a12beSStefan Roese } 81a47a12beSStefan Roese 82a47a12beSStefan Roese 83a47a12beSStefan Roese /* 84a47a12beSStefan Roese * Measure CPU clock speed (core clock GCLK1, GCLK2) 85a47a12beSStefan Roese * (Approx. GCLK frequency in Hz) 86a47a12beSStefan Roese */ 87a47a12beSStefan Roese get_clocks(void)88a47a12beSStefan Roeseint get_clocks(void) 89a47a12beSStefan Roese { 90a47a12beSStefan Roese sys_info_t sys_info; 91a47a12beSStefan Roese 92a47a12beSStefan Roese get_sys_info(&sys_info); 93997399faSPrabhakar Kushwaha gd->cpu_clk = sys_info.freq_processor; 94997399faSPrabhakar Kushwaha gd->bus_clk = sys_info.freq_systembus; 95997399faSPrabhakar Kushwaha gd->arch.lbc_clk = sys_info.freq_localbus; 96a47a12beSStefan Roese 97a47a12beSStefan Roese /* 98a47a12beSStefan Roese * The base clock for I2C depends on the actual SOC. Unfortunately, 99a47a12beSStefan Roese * there is no pattern that can be used to determine the frequency, so 100a47a12beSStefan Roese * the only choice is to look up the actual SOC number and use the value 101a47a12beSStefan Roese * for that SOC. This information is taken from application note 102a47a12beSStefan Roese * AN2919. 103a47a12beSStefan Roese */ 1041425a87bSYork Sun #ifdef CONFIG_ARCH_MPC8610 105997399faSPrabhakar Kushwaha gd->arch.i2c1_clk = sys_info.freq_systembus; 106a47a12beSStefan Roese #else 107997399faSPrabhakar Kushwaha gd->arch.i2c1_clk = sys_info.freq_systembus / 2; 108a47a12beSStefan Roese #endif 109609e6ec3SSimon Glass gd->arch.i2c2_clk = gd->arch.i2c1_clk; 110a47a12beSStefan Roese 111a47a12beSStefan Roese if (gd->cpu_clk != 0) 112a47a12beSStefan Roese return 0; 113a47a12beSStefan Roese else 114a47a12beSStefan Roese return 1; 115a47a12beSStefan Roese } 116a47a12beSStefan Roese 117a47a12beSStefan Roese 118a47a12beSStefan Roese /* 119a47a12beSStefan Roese * get_bus_freq 120a47a12beSStefan Roese * Return system bus freq in Hz 121a47a12beSStefan Roese */ 122a47a12beSStefan Roese get_bus_freq(ulong dummy)123a47a12beSStefan Roeseulong get_bus_freq(ulong dummy) 124a47a12beSStefan Roese { 125a47a12beSStefan Roese ulong val; 126a47a12beSStefan Roese sys_info_t sys_info; 127a47a12beSStefan Roese 128a47a12beSStefan Roese get_sys_info(&sys_info); 129997399faSPrabhakar Kushwaha val = sys_info.freq_systembus; 130a47a12beSStefan Roese 131a47a12beSStefan Roese return val; 132a47a12beSStefan Roese } 133