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/openbmc/u-boot/arch/arm/cpu/armv8/s32v234/
H A Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
8 #include <asm/arch/imx-regs.h>
20 u32 cpu = readl(&mscmir->cpxtype); in get_cpu_rev()
35 return -1; in get_pllfreq()
57 readl(DFS_DVPORTn(pll, selected_output - 1)); in get_pllfreq()
97 u32 freq = 0; in get_mcu_main_clk() local
107 switch (sysclk_sel) { in get_mcu_main_clk()
109 freq = FIRC_CLK_FREQ; in get_mcu_main_clk()
112 freq = XOSC_CLK_FREQ; in get_mcu_main_clk()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
69 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
77 clrsetbits_le32(&mxc_ccm->cscmr1, in set_usboh3_clk()
80 clrsetbits_le32(&mxc_ccm->cscdr1, in set_usboh3_clk()
91 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usboh3_clk()
107 return -EINVAL; in enable_i2c_clk()
111 setbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
113 clrbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
120 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); in set_usb_phy_clk()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dmax9867.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright 2013-2015 Maxim Integrated Products
6 // Copyright 2018 Ladislav Michl <ladis@linux-mips.org>
42 "Butterworth/8-24"
55 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max9867_adc_dac_event()
59 if (!strcmp(w->name, "ADCL")) in max9867_adc_dac_event()
61 else if (!strcmp(w->name, "ADCR")) in max9867_adc_dac_event()
63 else if (!strcmp(w->name, "DACL")) in max9867_adc_dac_event()
65 else if (!strcmp(w->name, "DACR")) in max9867_adc_dac_event()
71 max9867->adc_dac_active |= BIT(adc_dac); in max9867_adc_dac_event()
[all …]
H A Dmax98090.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
252 switch (reg) { in max98090_volatile_register()
265 switch (reg) { in max98090_readable_register()
279 /* Reset the codec by writing to this write-only reset register */ in max98090_reset()
280 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, in max98090_reset()
283 dev_err(max98090->component->dev, in max98090_reset()
300 -600, 600, 0);
303 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
[all …]
/openbmc/qemu/hw/misc/
H A Dimx6ul_ccm.c4 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
7 * See the COPYING file in the top-level directory.
82 switch (reg) { in imx6ul_ccm_reg_name()
155 switch (reg) { in imx6ul_analog_reg_name()
297 uint64_t freq = CKIH_FREQ; in imx6ul_analog_get_osc_clk() local
299 trace_ccm_freq((uint32_t)freq); in imx6ul_analog_get_osc_clk()
301 return freq; in imx6ul_analog_get_osc_clk()
306 uint64_t freq = imx6ul_analog_get_osc_clk(dev); in imx6ul_analog_get_pll2_clk() local
308 if (FIELD_EX32(dev->analog[CCM_ANALOG_PLL_SYS], in imx6ul_analog_get_pll2_clk()
310 freq *= 22; in imx6ul_analog_get_pll2_clk()
[all …]
H A Dimx31_ccm.c5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
8 * See the COPYING file in the top-level directory.
38 switch (reg) { in imx31_ccm_reg_name()
109 uint32_t freq = 0; in imx31_ccm_get_pll_ref_clk() local
112 if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) { in imx31_ccm_get_pll_ref_clk()
113 if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) { in imx31_ccm_get_pll_ref_clk()
114 freq = CKIL_FREQ; in imx31_ccm_get_pll_ref_clk()
115 if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) { in imx31_ccm_get_pll_ref_clk()
116 freq *= 1024; in imx31_ccm_get_pll_ref_clk()
120 freq = CKIH_FREQ; in imx31_ccm_get_pll_ref_clk()
[all …]
H A Dimx6_ccm.c4 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
7 * See the COPYING file in the top-level directory.
24 switch (reg) { in imx6_ccm_reg_name()
97 switch (reg) { in imx6_analog_reg_name()
247 uint64_t freq = 24000000; in imx6_analog_get_pll2_clk() local
249 if (EXTRACT(dev->analog[CCM_ANALOG_PLL_SYS], DIV_SELECT)) { in imx6_analog_get_pll2_clk()
250 freq *= 22; in imx6_analog_get_pll2_clk()
252 freq *= 20; in imx6_analog_get_pll2_clk()
255 trace_imx6_analog_get_pll2_clk(freq); in imx6_analog_get_pll2_clk()
257 return freq; in imx6_analog_get_pll2_clk()
[all …]
H A Dnpcm7xx_pwm.c19 #include "hw/qdev-clock.h"
20 #include "hw/qdev-properties.h"
25 #include "qemu/error-report.h"
75 uint32_t freq; in npcm7xx_pwm_calculate_freq() local
77 if (!p->running) { in npcm7xx_pwm_calculate_freq()
81 csr = NPCM7XX_CSR(p->module->csr, p->index); in npcm7xx_pwm_calculate_freq()
82 ppr = NPCM7XX_PPR(p->module->ppr, p->index); in npcm7xx_pwm_calculate_freq()
83 freq = clock_get_hz(p->module->clock); in npcm7xx_pwm_calculate_freq()
84 freq /= ppr + 1; in npcm7xx_pwm_calculate_freq()
92 /* freq won't be changed if csr == 4. */ in npcm7xx_pwm_calculate_freq()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
25 switch (frac_pll) { in decode_frac_pll()
27 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0); in decode_frac_pll()
28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
37 pllout_div = readl(&ana_pll->frac_pllout_div_cfg); in decode_frac_pll()
88 switch (sscg_pll) { in decode_sscg_pll()
98 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0); in decode_sscg_pll()
99 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
100 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2); in decode_sscg_pll()
[all …]
/openbmc/u-boot/arch/arm/mach-at91/armv7/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
3 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
7 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
27 switch (css) { in at91_css_to_rate()
31 return gd->arch.main_clk_rate_hz; in at91_css_to_rate()
33 return gd->arch.plla_rate_hz; in at91_css_to_rate()
39 static u32 at91_pll_rate(u32 freq, u32 reg) in at91_pll_rate() argument
46 freq /= div; in at91_pll_rate()
47 freq *= mul + 1; in at91_pll_rate()
49 freq = 0; in at91_pll_rate()
[all …]
/openbmc/linux/drivers/ssb/
H A Ddriver_chipcommon_pmu.c51 u16 freq; /* Crystal frequency in kHz.*/ member
58 { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
59 { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
60 { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
61 { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
62 { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
63 { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
64 { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
65 { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
66 { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/imx-regs.h>
11 #include <asm/mach-imx/sys_proto.h>
29 reg = readl(&ccm->ccgr6); in enable_ocotp_clk()
34 writel(reg, &ccm->ccgr6); in enable_ocotp_clk()
43 u32 freq = 0; in get_mcu_main_clk() local
45 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk()
49 ccm_cacrr = readl(&ccm->cacrr); in get_mcu_main_clk()
54 switch (sysclk_sel) { in get_mcu_main_clk()
56 freq = FASE_CLK_FREQ; in get_mcu_main_clk()
[all …]
/openbmc/linux/drivers/devfreq/
H A Dimx8m-ddrc.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
14 #include <linux/arm-smccc.h>
40 * +----------+ |\ +------+
41 * | dram_pll |-------|M| dram_core | |
42 * +----------+ |U|---------->| D |
43 * /--|X| | D |
46 * +---------+ | |
48 * +---------+ | |
50 * +----------+ | | |
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dtda18271-fe.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
9 #include "tda18271-priv.h"
17 MODULE_PARM_DESC(debug, "set debug level (info=1, map=2, reg=4, adv=8, cal=16 (or-able))");
19 static int tda18271_cal_on_startup = -1;
26 /*---------------------------------------------------------------------*/
30 struct tda18271_priv *priv = fe->tuner_priv; in tda18271_toggle_output()
33 priv->output_opt & TDA18271_OUTPUT_LT_OFF ? 1 : 0, in tda18271_toggle_output()
34 priv->output_opt & TDA18271_OUTPUT_XT_OFF ? 1 : 0); in tda18271_toggle_output()
41 priv->output_opt & TDA18271_OUTPUT_XT_OFF ? "off" : "on", in tda18271_toggle_output()
[all …]
/openbmc/linux/net/wireless/
H A Dchan.c1 // SPDX-License-Identifier: GPL-2.0
8 * Copyright 2013-2014 Intel Mobile Communications GmbH
9 * Copyright 2018-2022 Intel Corporation
16 #include "rdev-ops.h"
18 static bool cfg80211_valid_60g_freq(u32 freq) in cfg80211_valid_60g_freq() argument
20 return freq >= 58320 && freq <= 70200; in cfg80211_valid_60g_freq()
30 chandef->chan = chan; in cfg80211_chandef_create()
31 chandef->freq1_offset = chan->freq_offset; in cfg80211_chandef_create()
32 chandef->center_freq2 = 0; in cfg80211_chandef_create()
33 chandef->edmg.bw_config = 0; in cfg80211_chandef_create()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
10 #include <asm/arch/imx-regs.h>
31 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
36 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
44 clrbits_le32(&imx_ccm->CCGR4, in setup_gpmi_io_clk()
52 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk()
54 clrsetbits_le32(&imx_ccm->cs2cdr, in setup_gpmi_io_clk()
60 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk()
62 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_io_clk()
[all …]
/openbmc/qemu/hw/timer/
H A Dsh_timer.c6 * Copyright (c) 2005-2006 CodeSourcery.
42 int freq; member
54 int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); in sh_timer_update()
56 if (new_level != s->old_level) { in sh_timer_update()
57 qemu_set_irq(s->irq, new_level); in sh_timer_update()
59 s->old_level = s->int_level; in sh_timer_update()
60 s->int_level = new_level; in sh_timer_update()
67 switch (offset >> 2) { in sh_timer_read()
69 return s->tcor; in sh_timer_read()
71 return ptimer_get_count(s->timer); in sh_timer_read()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
30 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in get_clocks()
32 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in get_clocks()
34 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in get_clocks()
113 switch (pll) { in decode_pll()
115 reg = readl(&ccm_anatop->pll_arm); in decode_pll()
129 reg = readl(&ccm_anatop->pll_480); in decode_pll()
144 reg = readl(&ccm_anatop->pll_enet); in decode_pll()
155 reg = readl(&ccm_anatop->pll_ddr); in decode_pll()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv50.c34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
60 switch (device->chipset) { in read_pll_src()
63 switch (base) { in read_pll_src()
91 switch (base) { in read_pll_src()
101 switch (rsel) { in read_pll_src()
103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
[all …]
H A Dgk104.c33 u32 freq; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
74 switch (pll) { in read_pll()
77 sclk = device->crystal; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
112 switch (ssrc & 0x00000003) { in read_div()
115 return device->crystal; in read_div()
135 struct nvkm_device *device = clk->base.subdev.device; in read_mem()
136 switch (nvkm_rd32(device, 0x1373f4) & 0x0000000f) { in read_mem()
[all …]
/openbmc/linux/sound/pci/lola/
H A Dlola_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for Digigram Lola PCI-e boards
17 unsigned int freq; in lola_sample_rate_convert() local
20 switch (coded & 0x3) { in lola_sample_rate_convert()
21 case 0: freq = 48000; break; in lola_sample_rate_convert()
22 case 1: freq = 44100; break; in lola_sample_rate_convert()
23 case 2: freq = 32000; break; in lola_sample_rate_convert()
28 switch (coded & 0x1c) { in lola_sample_rate_convert()
31 case (1 << 2): freq *= 2; break; in lola_sample_rate_convert()
32 case (2 << 2): freq *= 4; break; in lola_sample_rate_convert()
[all …]
/openbmc/linux/drivers/media/i2c/cx25840/
H A Dcx25840-audio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <media/v4l2-common.h>
9 #include <media/drv-intf/cx25840.h>
11 #include "cx25840-core.h"
17 * NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
31 static int cx25840_set_audclk_freq(struct i2c_client *client, u32 freq) in cx25840_set_audclk_freq() argument
35 if (state->aud_input != CX25840_AUDIO_SERIAL) { in cx25840_set_audclk_freq()
36 switch (freq) { in cx25840_set_audclk_freq()
47 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
53 * 196.6 MHz pre-postdivide in cx25840_set_audclk_freq()
[all …]
/openbmc/qemu/hw/audio/
H A Dsb16.c4 * Copyright (c) 2003-2005 Vassili Karpov (malc)
30 #include "hw/qdev-properties.h"
33 #include "qemu/host-utils.h"
77 int freq; member
125 switch (irq) { in magic_of_irq()
142 switch (magic) { in irq_of_magic()
153 return -1; in irq_of_magic()
160 ldebug ("%s:%s:%d:%s:dmasize=%d:freq=%d:const=%d:speaker=%d\n",
161 dsp->fmt_stereo ? "Stereo" : "Mono",
162 dsp->fmt_signed ? "Signed" : "Unsigned",
[all …]
/openbmc/linux/sound/soc/ti/
H A Domap-dmic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-dmic.c -- OMAP ASoC DMIC DAI driver
5 * Copyright (C) 2010 - 2011 Texas Instruments
30 #include "omap-dmic.h"
31 #include "sdma-pcm.h"
53 writel_relaxed(val, dmic->io_base + reg); in omap_dmic_write()
58 return readl_relaxed(dmic->io_base + reg); in omap_dmic_read()
69 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled); in omap_dmic_start()
96 mutex_lock(&dmic->mutex); in omap_dmic_dai_startup()
99 dmic->active = 1; in omap_dmic_dai_startup()
[all …]
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2012-2014
46 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) in wait_for_completion()
53 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | in bypass_main_pll()
64 pllm = data->pll_m - 1; in configure_mult_div()
65 plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK; in configure_mult_div()
68 if (data->pll == MAIN_PLL) in configure_mult_div()
69 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); in configure_mult_div()
71 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
76 bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */ in configure_mult_div()
[all …]

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