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/openbmc/linux/arch/m68k/ifpsp060/
H A Dos.S3 |M68000 Hi-Performance Microprocessor Division
5 |Production Release P1.00 -- October 10, 1994
32 | - example "Call-Out"s required by both the ISP and FPSP.
38 | EXAMPLE CALL-OUTS #
58 | or supervisor application space. The examples below use simple "move"
59 | instructions for supervisor mode applications and call _copyin()/_copyout()
60 | for user mode applications.
76 | Writes to data memory while in supervisor mode.
79 | a0 - supervisor source address
80 | a1 - user destination address
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H A DCHANGES3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
31 ---------------------------
42 mode was pre-decrement or post-increment and the address register
49 ---------
56 -------
66 ----
70 ------
71 Upon receiving a non-zero (failing) return value from
72 a {i,d}mem_{read,write}_{byte,word,long}() "call-out",
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/openbmc/linux/arch/m68k/fpsp040/
H A Dskeleton.S37 | Modified for Linux-1.3.x by Jes Sorensen (jds@kom.auc.dk)
42 #include <asm/asm-offsets.h>
66 link %a6,#-LOCAL_SIZE
67 fsave -(%sp)
74 movel %sp,%sp@- | stack frame pointer argument
103 link %a6,#-LOCAL_SIZE
104 fsave -(%sp)
107 fmovel %fpsr,-(%sp)
142 link %a6,#-LOCAL_SIZE
143 fsave -(%sp)
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
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/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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/openbmc/linux/arch/m68k/include/asm/
H A Dm54xxacr.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
35 #define ACR_USER 0x00000000 /* User mode access only */
36 #define ACR_SUPER 0x00002000 /* Supervisor mode only */
37 #define ACR_ANY 0x00004000 /* Match any access mode */
38 #define ACR_CM_WT 0x00000000 /* Write through mode */
39 #define ACR_CM_CP 0x00000020 /* Copyback mode */
42 #define ACR_CM 0x00000060 /* Cache mode mask */
43 #define ACR_SP 0x00000008 /* Supervisor protect */
47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
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H A Dmcfdma.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfdma.h -- Coldfire internal DMA support defines.
73 #define MCFDMA_DMR 0x00 /* Mode Register (r/w) */
79 /* Bit definitions for the DMA Mode Register (DMR) */
82 #define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */
83 #define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */
89 #define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */
90 #define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */
101 #define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */
102 #define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */
H A Dmcfmmu.h2 * mcfmmu.h -- definitions for the ColdFire v4e MMU
35 #define MMUCR_EN 0x00000001 /* Virtual mode enable */
36 #define MMUCR_ASM 0x00000002 /* Address space mode */
47 #define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */
48 #define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */
60 #define MMUSR_SPF 0x00000020 /* Supervisor protect fault */
79 #define MMUDR_SP 0x00000020 /* Supervisor access enable */
82 #define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */
83 #define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */
H A Dmotorola_pgtable.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define _PAGE_SUPER 0x080 /* 68040 supervisor only */
17 #define _PAGE_NOCACHE030 0x040 /* 68030 no-cache mode */
18 #define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */
19 #define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */
20 #define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */
21 #define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */
31 * 3 - Used
32 * 2 - Write Protected
33 * 0,1 - Descriptor Type
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/openbmc/linux/Documentation/hwmon/
H A Dsl28cpld.rst1 .. SPDX-License-Identifier: GPL-2.0-only
17 -----------
21 supervisor. In the future there might be other flavours and additional
24 The fan supervisor has a 7 bit counter register and a counter period of 1
25 second. If the 7 bit counter overflows, the supervisor will automatically
26 switch to x8 mode to support a wider input range at the loss of
30 -------------
/openbmc/linux/arch/riscv/include/asm/
H A Dcsr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
39 #define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Poin
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/openbmc/linux/arch/microblaze/include/asm/
H A Dmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
27 unsigned long w:1; /* Write-thru cache mode */
36 # define PP_RWXX 0 /* Supervisor read/write, User none */
37 # define PP_RWRX 1 /* Supervisor read/write, User read */
38 # define PP_RWRW 2 /* Supervisor read/write, User read/write */
39 # define PP_RXRX 3 /* Supervisor read, User read */
44 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
46 unsigned long n:1; /* No-execute */
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/openbmc/qemu/target/riscv/
H A Dcpu_bits.h1 /* RISC-V ISA constants */
15 /* Floating point round mode */
52 /* User Floating-Point CSRs */
160 /* 32-bit only */
172 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
176 /* Machine-Level Interrupts (AIA) */
180 /* Virtual Interrupts for Supervisor Level (AIA) */
184 /* Machine-Level High-Half CSRs (AIA) */
191 /* Supervisor Trap Setup */
197 /* Supervisor Configuration CSRs */
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/openbmc/linux/arch/powerpc/include/asm/book3s/32/
H A Dmmu-hash.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * 32-bit hash table MMU support
57 #define PP_RWXX 0 /* Supervisor read/write, User none */
58 #define PP_RWRX 1 /* Supervisor read/write, User read */
59 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
60 #define PP_RXRX 3 /* Supervisor read, User read */
65 #define SR_KS 0x40000000 /* Supervisor key */
69 #include <asm/asm-offsets.h>
147 * of the 32-bit virtual address (the "effective segment ID") in order
165 unsigned long xpn:3; /* Real page number bits 0-2, optional */
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/openbmc/linux/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
215 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */
231 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
269 #define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
270 #define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
275 #define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
276 #define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
295 #define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
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/openbmc/u-boot/arch/arm/mach-imx/
H A Dinit.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/imx-regs.h>
10 #include <asm/mach-imx/boot_mode.h>
22 * Set all MPROTx to be non-bufferable, trusted for R/W, in init_aips()
23 * not forced to user-mode. in init_aips()
25 writel(0x77777777, &aips1->mprot0); in init_aips()
26 writel(0x77777777, &aips1->mprot1); in init_aips()
27 writel(0x77777777, &aips2->mprot0); in init_aips()
28 writel(0x77777777, &aips2->mprot1); in init_aips()
31 * Set all OPACRx to be non-bufferable, not require in init_aips()
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/openbmc/u-boot/arch/powerpc/include/asm/
H A Dmmu.h28 unsigned long w:1; /* Write-thru cache mode */
37 #define PP_RWXX 0 /* Supervisor read/write, User none */
38 #define PP_RWRX 1 /* Supervisor read/write, User read */
39 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
40 #define PP_RXRX 3 /* Supervisor read, User read */
45 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
47 unsigned long n:1; /* No-execute */
59 unsigned long ks:1; /* Supervisor key (normally 0) */
72 unsigned long vs:1; /* Supervisor valid */
90 unsigned long w:1; /* Write-thru cache */
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/openbmc/qemu/tests/tcg/s390x/
H A Dlpsw.S4 * SPDX-License-Identifier: GPL-2.0-or-later
8 .org 0x1c0 /* supervisor call new PSW */
9 .quad 0x80000000,svc /* 31-bit mode */
30 64-bit mode */
/openbmc/linux/arch/x86/kernel/fpu/
H A Dsignal.c1 // SPDX-License-Identifier: GPL-2.0
35 if (__copy_from_user(fx_sw, &fxbuf->sw_reserved[0], sizeof(*fx_sw))) in check_xstate_in_sigframe()
39 if (fx_sw->magic1 != FP_XSTATE_MAGIC1 || in check_xstate_in_sigframe()
40 fx_sw->xstate_size < min_xstate_size || in check_xstate_in_sigframe()
41 fx_sw->xstate_size > current->thread.fpu.fpstate->user_size || in check_xstate_in_sigframe()
42 fx_sw->xstate_size > fx_sw->extended_size) in check_xstate_in_sigframe()
51 if (__get_user(magic2, (__u32 __user *)(fpstate + fx_sw->xstate_size))) in check_xstate_in_sigframe()
57 trace_x86_fpu_xstate_check_failed(&current->thread.fpu); in check_xstate_in_sigframe()
60 fx_sw->magic1 = 0; in check_xstate_in_sigframe()
61 fx_sw->xstate_size = sizeof(struct fxregs_state); in check_xstate_in_sigframe()
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H A Dxstate.c1 // SPDX-License-Identifier: GPL-2.0-only
47 "AVX-512 opmask",
48 "AVX-512 Hi256",
49 "AVX-512 ZMM_Hi256",
53 "Control-flow User registers",
54 "Control-flow Kernel registers (unused)",
82 { [ 0 ... XFEATURE_MAX - 1] = -1};
84 { [ 0 ... XFEATURE_MAX - 1] = -1};
106 * missing AVX feature - this is the most informative message in cpu_has_xfeatures()
114 xfeature_idx = fls64(xfeatures_print)-1; in cpu_has_xfeatures()
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/openbmc/linux/arch/sparc/include/asm/
H A Diommu_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
31 volatile unsigned long afsr; /* Async-fault status register */
32 volatile unsigned long afar; /* Async-fault physical address */
34 volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
38 volatile unsigned long mfsr; /* Memory-fault status register */
39 volatile unsigned long mfar; /* Memory-fault physical address */
42 volatile unsigned long mid; /* IOMMU module-id */
48 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
49 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
50 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
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H A Dross.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 * -----------------------------------------------------------------
22 * -----------------------------------------------------------------
23 * 31 24 23-22 21 20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
25 * Phew, lots of fields there ;-)
31 * BM: Boot-Mode. One indicates the MMU is in boot mode.
34 * CS: Cache Size -- 0 = 128k, 1 = 256k
37 * CM: Cache Mode -- 0 = write-through, 1 = copy-back
38 * CE: Cache Enable -- 0 = no caching, 1 = cache is on
39 * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
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/openbmc/u-boot/arch/riscv/
H A DKconfig1 menu "RISC-V architecture"
12 bool "Support ax25-ae350"
22 # board-specific options below
23 source "board/AndesTech/ax25-ae350/Kconfig"
24 source "board/emulation/qemu-riscv/Kconfig"
27 # platform-specific options below
31 # architecture-specific options below
59 U-Boot and its statically defined symbols must lie within a single 2 GiB
60 address range and must lie between absolute addresses -2 GiB and +2 GiB.
65 U-Boot and its statically defined symbols must be within any single 2 GiB
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/openbmc/qemu/target/alpha/
H A Dcpu.h23 #include "cpu-qom.h"
24 #include "exec/cpu-defs.h"
25 #include "qemu/cpu-float.h"
108 /* IEEE floating-point operations encoding */
109 /* Trap mode */
118 /* Rounding mode */
126 /* FPCR bits -- right-shifted 32 so we can use a uint32_t. */
127 #define FPCR_SUM (1U << (63 - 32))
128 #define FPCR_INED (1U << (62 - 32))
129 #define FPCR_UNFD (1U << (61 - 32))
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/openbmc/linux/Documentation/virt/kvm/x86/
H A Dhypercalls.rst1 .. SPDX-License-Identifier: GPL-2.0
8 KVM Hypercalls have a three-byte sequence of either the vmcall or the vmmcall
18 R2-R7 are used for parameters 1-6. In addition, R1 is used for hypercall
25 refer to Documentation/virt/kvm/s390/s390-diag.rst.
28 It uses R3-R10 and hypercall number in R11. R4-R11 are used as output registers.
31 KVM hypercalls uses 4 byte opcode, that are patched with 'hypercall-instructions'
33 For more information refer to Documentation/virt/kvm/ppc-pv.rst
37 number in $2 (v0). Up to four arguments may be placed in $4-$7 (a0-a3) and
50 ------------------------
58 ----------------
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