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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dst,stm32-exti.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stm32-exti.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STM32 External Interrupt Controller
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Ludovic Barre <ludovic.barre@foss.st.com>
16 - items:
17 - enum:
18 - st,stm32-exti
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp131.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/reset/stm32mp13-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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H A Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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H A Dstm32h743.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32h7-clks.h>
45 #include <dt-bindings/mfd/stm32h7-rcc.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
53 clk_hse: clk-hse {
54 #clock-cells = <0>;
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H A Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
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H A Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
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H A Dstm32f7-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
7 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
8 #include <dt-bindings/mfd/stm32f7-rcc.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&exti>;
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
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H A Dstm32f4-pinctrl.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
44 #include <dt-bindings/mfd/stm32f4-rcc.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
52 interrupt-parent = <&exti>;
56 gpio-controller;
57 #gpio-cells = <2>;
58 interrupt-controller;
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
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/openbmc/qemu/docs/system/arm/
H A Dstm32.rst1 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vl…
4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
12 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
17 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller
19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4
20 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with STM32F2 series.
21 The following machines are based on this ARM Cortex-M4F chip :
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H A Db-l475e-iot01a.rst1 B-L475E-IOT01A IoT Node (``b-l475e-iot01a``)
4 The B-L475E-IOT01A IoT Node uses the STM32L475VG SoC which is based on
5 ARM Cortex-M4F core. It is part of STMicroelectronics
6 :doc:`STM32 boards </system/arm/stm32>` and more specifically the STM32L4
7 ultra-low power series. The STM32L4x5 chip runs at up to 80 MHz and
8 integrates 128 KiB of SRAM and up to 1MiB of Flash. The B-L475E-IOT01A board
15 Currently B-L475E-IOT01A machines support the following devices:
17 - Cortex-M4F based STM32L4x5 SoC
18 - STM32L4x5 EXTI (Extended interrupts and events controller)
19 - STM32L4x5 SYSCFG (System configuration controller)
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/openbmc/u-boot/arch/arm/dts/
H A Dstm32f429.dtsi2 * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
3 * Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
5 * This file is dual-licensed: you can use it either under the terms
45 #include "armv7-m.dtsi"
46 #include <dt-bindings/clock/stm32fx-clock.h>
47 #include <dt-bindings/mfd/stm32f4-rcc.h>
51 clk_hse: clk-hse {
52 #clock-cells = <0>;
53 compatible = "fixed-clock";
54 clock-frequency = <0>;
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H A Dstm32mp157c.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
[all …]
H A Dstm32mp157-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
10 pinctrl: pin-controller@50002000 {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "st,stm32mp157-pinctrl";
15 interrupt-parent = <&exti>;
16 st,syscfg = <&exti 0x60 0xff>;
17 pins-are-numbered;
[all …]
H A Dstm32f4-pinctrl.dtsi2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
45 #include <dt-bindings/mfd/stm32f4-rcc.h>
49 pinctrl: pin-controller {
50 #address-cells = <1>;
51 #size-cells = <1>;
53 interrupt-parent = <&exti>;
55 pins-are-numbered;
58 gpio-controller;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: STM32 GPIO and Pin Mux/Config controller
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
[all …]
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dst,stm32-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Real Time Clock
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
15 - st,stm32-rtc
16 - st,stm32h7-rtc
17 - st,stm32mp1-rtc
26 clock-names:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dst,stm32-ipcc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 IPC controller
16 - Fabien Dessenne <fabien.dessenne@foss.st.com>
17 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
21 const: st,stm32mp1-ipcc
31 - description: rx channel occupied
32 - description: tx channel free
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-adc-stm325 The STM32 ADC can be configured to use external trigger sources
6 (e.g. timers, pwm or exti gpio). Then, it can be tuned to start
9 - "rising-edge"
10 - "falling-edge"
11 - "both-edges".
/openbmc/linux/drivers/irqchip/
H A Dirq-stm32-exti.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
24 #include <dt-bindings/interrupt-controller/arm-gic.h>
184 __diag_ignore_all("-Woverride-init",
189 [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
238 [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
297 struct stm32_exti_chip_data *chip_data = gc->private; in stm32_exti_pending()
298 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; in stm32_exti_pending()
301 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); in stm32_exti_pending()
302 if (stm32_bank->fpr_ofst != UNDEF_REG) in stm32_exti_pending()
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
[all …]
/openbmc/linux/
H A Dopengrok2.0.log1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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