| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | marvell,kirkwood-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
25 mpp1 1 gpo, nand(io3), spi(mosi)
26 mpp2 2 gpo, nand(io4), spi(sck)
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| H A D | lantiq,pinctrl-xway.txt | 4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is:
10 - reg: Should contain the physical address and length of the gpio/pinmux
13 Please refer to pinctrl-bindings.txt in this directory for details of the
21 pull-up and open-drain
36 Required subnode-properties:
37 - lantiq,groups : An array of strings. Each string contains the name of a group.
39 - lantiq,function: A string containing the name of the function to mux to the
51 spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
56 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
62 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
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| /openbmc/u-boot/include/linux/mtd/ |
| H A D | spinand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
16 #include <linux/mtd/nand.h>
17 #include <linux/spi/spi.h>
18 #include <linux/spi/spi-mem.h>
21 #include <spi.h>
22 #include <spi-mem.h>
23 #include <linux/mtd/nand.h>
27 * Standard SPI NAND flash operations
121 * Standard SPI NAND flash commands
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| /openbmc/linux/include/linux/mtd/ |
| H A D | spinand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
15 #include <linux/mtd/nand.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi-mem.h>
20 * Standard SPI NAND flash operations
144 * Standard SPI NAND flash commands
197 * struct spinand_id - SPI NAND id structure
214 * struct spinand_devid - SPI NAND device id structure
222 * read_id opcode + 1-byte address.
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | mediatek,spi-mtk-snfi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
14 the Mediatek NAND flash controller. It can perform standard SPI
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
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| H A D | mxicy,mx25f0a-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mxicy,mx25f0a-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Macronix SPI controller
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: spi-controller.yaml#
17 const: mxicy,mx25f0a-spi
23 reg-names:
25 - const: regs
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| /openbmc/u-boot/arch/arm/mach-uniphier/boot-device/ |
| H A D | boot-device-pxs2.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2017 Socionext Inc.
12 #include "boot-device.h"
15 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
[all …]
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| /openbmc/linux/drivers/mtd/nand/spi/ |
| H A D | core.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Micron Technology, Inc.
10 #define pr_fmt(fmt) "spi-nand: " fmt
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi-mem.h>
26 spinand->scratchbuf); in spinand_read_reg_op()
29 ret = spi_mem_exec_op(spinand->spimem, &op); in spinand_read_reg_op()
33 *val = *spinand->scratchbuf; in spinand_read_reg_op()
40 spinand->scratchbuf); in spinand_write_reg_op()
42 *spinand->scratchbuf = val; in spinand_write_reg_op()
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | mxicy,nand-ecc-engine.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Macronix NAND ECC engine
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 const: mxicy,nand-ecc-engine-rev3
26 - compatible
27 - reg
32 - |
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| H A D | spi-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/spi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
18 const: spi-nand
21 description: Encode the chip-select line on the SPI bus
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| /openbmc/u-boot/drivers/mtd/nand/spi/ |
| H A D | core.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Micron Technology, Inc.
10 #define pr_fmt(fmt) "spi-nand: " fmt
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi-mem.h>
25 #include <spi.h>
26 #include <spi-mem.h>
30 /* SPI NAND index visible in MTD names */
37 struct nand_device *nand = spinand_to_nand(spinand); in spinand_cache_op_adjust_colum() local
40 if (nand->memorg.planes_per_lun < 2) in spinand_cache_op_adjust_colum()
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| /openbmc/u-boot/doc/ |
| H A D | README.at91 | 4 - I. Board mapping & boot media
5 - II. NAND partition table
6 - III. watchdog support
9 ------------------------------------------------------------------------------
11 ------------------------------------------------------------------------------
14 0x20000000 - 23FFFFFF SDRAM (64 MB)
15 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J13)
16 0xD0000000 - D07FFFFF Soldered Atmel Dataflash (AT45DB642)
20 U-Boot environment variables can be stored at different places:
21 - Dataflash on SPI chip select 1 (default)
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| /openbmc/linux/drivers/pinctrl/ |
| H A D | pinctrl-xway.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-xway.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
21 #include "pinctrl-lantiq.h"
110 /* --------- ase related code --------- */
122 MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
123 MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
124 MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
125 MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
129 MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
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| /openbmc/u-boot/board/phytec/pcm058/ |
| H A D | README | 2 -----------------
5 The SOM is sold in two versions, with eMMC or with NAND. Support
6 here is for the SOM with NAND.
7 The evaluation board "phyBoard-Mira" is thought to be used
13 http://www.phytec.de/produkt/single-board-computer/phyboard-mira/
14 http://www.phytec.de/fileadmin/user_upload/images/content/1.Products/SOMs/phyCORE-i.MX6/L-808e_1.pdf
16 Building U-Boot
17 -------------------------------
22 This generates the artifacts SPL and u-boot.img.
23 The SOM can boot from NAND or from SD-Card, having the SPI-NOR
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| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PA | 5 The P1010 is a cost-effective, low-power, highly integrated host processor
14 - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15 - 32 Mbyte NOR flash single-chip memory
16 - 32 Mbyte NAND flash memory
17 - 256 Kbit M24256 I2C EEPROM
18 - 16 Mbyte SPI memory
19 - I2C Board EEPROM 128x8 bit memory
20 - SD/MMC connector to interface with the SD memory card
22 - PCIe:
23 - Lane0: x1 mini-PCIe slot
[all …]
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| H A D | README.P1010RDB-PB | 3 The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
4 P1010RDB-PB is a variation of previous P1010RDB-PA board.
6 The P1010 is a cost-effective, low-power, highly integrated host processor
13 The P1010RDB-PB board features are as following:
15 - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
16 - 32M bytes NOR flash single-chip memory
17 - 2G bytes NAND flash memory
18 - 16M bytes SPI memory
19 - 256K bit M24256 I2C EEPROM
20 - I2C Board EEPROM 128x8 bit memory
[all …]
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| /openbmc/u-boot/doc/mvebu/cmd/ |
| H A D | bubt.txt | 2 --------------------------
6 bubt [file-name] [destination [source]]
7 - file-name Image file name to burn. default = flash-image.bin
8 - destination Flash to burn to [spi, nand, mmc]. default = active flash
9 - source Source to load image from [tftp, usb]. default = tftp
12 bubt - Burn flash-image.bin from tftp to active flash
13 bubt latest-spi.bin nand - Burn latest-spi.bin from tftp to NAND flash
16 - For the TFTP interface set serverip and ipaddr.
17 - To burn image to SD/eMMC device, the target is defined
20 Bubt command details (burn image step by-step)
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| /openbmc/linux/arch/powerpc/boot/dts/fsl/ |
| H A D | mpc8536ds.dtsi | 2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
52 read-only;
57 label = "dink-nor";
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| H A D | p1024rdb.dtsi | 2 * P1024 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
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| H A D | p2020rdb.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2009-2012 Freescale Semiconductor Inc.
8 /include/ "p2020si-pre.dtsi"
31 /* NOR and NAND Flashes */
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR (RO) Vitesse-7385 Firmware";
[all …]
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| H A D | p2020rdb-pc.dtsi | 2 * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
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| H A D | p1021rdb-pc.dtsi | 2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
75 read-only;
80 /* 512KB for u-boot Bootloader Image */
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| H A D | p1022ds.dtsi | 2 * P1022 DS Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
47 read-only;
52 label = "diagnostic-nor";
53 read-only;
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| /openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/ |
| H A D | ns2-svk.dts | 33 /dts-v1/;
39 compatible = "brcm,ns2-svk", "brcm,ns2";
49 stdout-path = "serial0:115200n8";
113 spi-max-frequency = <5000000>;
114 spi-cpha;
115 spi-cpol;
118 pl022,slave-tx-disable = <0>;
119 pl022,com-mode = <0>;
120 pl022,rx-level-trig = <1>;
121 pl022,tx-level-trig = <1>;
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| /openbmc/u-boot/board/davinci/da8xxevm/ |
| H A D | README.da850 | 6 In the context of U-Boot, the board is booted in three stages. The initial
10 controller (such as SPI or NAND) to continue the boot process by loading
12 further (some clocks, SDRAM) and then load the full u-boot from a
13 predefined location in persistent storage to DDR and jumps to the u-boot
24 it allows for additional flexibility (run-time detect of board revision,
32 the end of SPI flash, run 'make da850evm'. For boards which store the
35 u-boot.ais file that needs to be written to the correct persistent
39 Flashing the images to SPI
41 The AIS image can be written to SPI flash using the following commands.
42 Assuming that the network is configured and enabled and the u-boot.ais file
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