Lines Matching +full:spi +full:- +full:nand
3 The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
4 P1010RDB-PB is a variation of previous P1010RDB-PA board.
6 The P1010 is a cost-effective, low-power, highly integrated host processor
13 The P1010RDB-PB board features are as following:
15 - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
16 - 32M bytes NOR flash single-chip memory
17 - 2G bytes NAND flash memory
18 - 16M bytes SPI memory
19 - 256K bit M24256 I2C EEPROM
20 - I2C Board EEPROM 128x8 bit memory
21 - SD/MMC connector to interface with the SD memory card
23 - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
24 - PCIe 2.0: two x1 mini-PCIe slots
25 - SATA 2.0: two SATA interfaces
26 - USB 2.0: one USB interface
27 - FlexCAN: two FlexCAN interfaces (revision 2.0B)
28 - UART: one USB-to-Serial interface
29 - TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
33 - Mini-ITX power supply connector
34 - JTAG/COP for debugging
37 PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
43 0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
44 0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
45 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
46 0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
47 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
49 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
55 -Data rate: 115200 bps
56 -Number of data bits: 8
57 -Parity: None
58 -Number of Stop bits: 1
59 -Flow Control: Hardware/None
62 P1010RDB-PB default DIP-switch settings
71 P1010RDB-PB boot mode settings via DIP-switch
74 SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
75 SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
80 Switch P1010RDB-PB boot mode via software without setting DIP-switch
84 => run boot_nand (boot from NAND flash)
85 => run boot_spi (boot from SPI flash)
89 Frequency combination support on P1010RDB-PB
102 Since pins multiplexing, TDM and CAN are muxed with SPI flash.
103 SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
113 To enable SDHC in case of NOR/NAND/SPI boot
115 run 'mux sdhc' in U-Boot to validate SDHC with invalidating IFC.
117 b) For long-term use case
122 run 'mux ifc' in U-Boot to validate IFC with invalidating SDHC.
124 b) For long-term use case
132 $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
135 $ make P1010RDB-PB_NOR
137 2. For NAND boot
138 $ make P1010RDB-PB_NAND
140 3. For SPI boot
141 $ make P1010RDB-PB_SPIFLASH
144 $ make P1010RDB-PB_SDCARD
150 => tftp 1000000 u-boot.bin
159 2. NAND boot
160 => tftp 1000000 u-boot-nand.bin
161 => nand erase 0 $filesize; nand write $loadaddr 0 $filesize
164 3. SPI boot
165 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
166 2) => tftp 1000000 u-boot-spi-combined.bin
171 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
172 2) => tftp 1000000 u-boot-sd-combined.bin
178 Boot Linux from network using TFTP on P1010RDB-PB
187 For more details, please refer to P1010RDB-PB User Guide and access website