| /openbmc/linux/drivers/spi/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # SPI driver configuration
5 menuconfig SPI config
6 bool "SPI support"
10 protocol. Chips that support SPI can have data transfer rates
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
15 SPI is widely used by microcontrollers to talk with sensors,
16 eeprom and flash memory, codecs and various other controller
17 chips, analog to digital (and d-to-a) converters, and more.
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| H A D | spi-loongson-core.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // Loongson SPI Support
14 #include <linux/spi/spi.h>
16 #include "spi-loongson.h"
18 static inline void loongson_spi_write_reg(struct loongson_spi *spi, unsigned char reg, in loongson_spi_write_reg() argument
21 writeb(data, spi->base + reg); in loongson_spi_write_reg()
24 static inline char loongson_spi_read_reg(struct loongson_spi *spi, unsigned char reg) in loongson_spi_read_reg() argument
26 return readb(spi->base + reg); in loongson_spi_read_reg()
29 static void loongson_spi_set_cs(struct spi_device *spi, bool en) in loongson_spi_set_cs() argument
32 unsigned char mask = (BIT(4) | BIT(0)) << spi_get_chipselect(spi, 0); in loongson_spi_set_cs()
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| H A D | spi-stm32.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
20 #include <linux/spi/spi.h>
24 /* STM32F4 SPI registers */
73 /* STM32F4 SPI Baud Rate min/max divisor */
77 /* STM32H7 SPI registers */
149 /* STM32H7 SPI Master Baud Rate min/max divisor */
153 /* STM32H7 SPI Communication mode */
159 /* SPI Communication type */
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| H A D | spi-mux.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // General Purpose SPI multiplexer
10 #include <linux/spi/spi.h>
12 #define SPI_MUX_NO_CS ((unsigned int)-1)
17 * This driver supports a MUX on an SPI bus. This can be useful when you need
21 * The driver will create an additional SPI controller. Devices added under the
22 * mux will be handled as 'chip selects' on this controller.
26 * struct spi_mux_priv - the basic spi_mux structure
27 * @spi: pointer to the device struct attached to the parent
28 * spi controller
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| H A D | spi-microchip-core.c | 1 // SPDX-License-Identifier: (GPL-2.0)
3 * Microchip CoreSPI SPI controller driver
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
21 #include <linux/spi/spi.h>
108 u32 clk_gen; /* divider for spi output clock generated by the controller */
117 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg) in mchp_corespi_read() argument
119 return readl(spi->regs + reg); in mchp_corespi_read()
122 static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val) in mchp_corespi_write() argument
124 writel(val, spi->regs + reg); in mchp_corespi_write()
127 static inline void mchp_corespi_disable(struct mchp_corespi *spi) in mchp_corespi_disable() argument
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| H A D | spi-qup.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
16 #include <linux/spi/spi.h>
18 #include <linux/dma-mapping.h>
115 #define SPI_MAX_XFER (SZ_64K - 64)
140 int w_size; /* bytes per SPI word */
153 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer);
155 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) in spi_qup_is_flag_set() argument
157 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
171 static inline unsigned int spi_qup_len(struct spi_qup *controller) in spi_qup_len() argument
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| H A D | spi-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cadence SPI controller driver (host and target mode)
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
21 #include <linux/spi/spi.h>
24 #define CDNS_SPI_NAME "cdns-spi"
41 * SPI Configuration Register bit Masks
44 * of the SPI controller
62 * SPI Configuration Register - Baud rate and target select
76 * SPI Interrupt Registers bit Masks
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| H A D | spi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // SPI init/core code
9 #include <linux/clk/clk-conf.h>
13 #include <linux/dma-mapping.h>
34 #include <linux/spi/spi.h>
35 #include <linux/spi/spi-mem.h>
39 #include <trace/events/spi.h>
49 struct spi_device *spi = to_spi_device(dev); in spidev_release() local
51 spi_controller_put(spi->controller); in spidev_release()
52 kfree(spi->driver_override); in spidev_release()
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| H A D | spi-davinci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/dma-mapping.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/spi_bitbang.h>
22 #include <linux/platform_data/spi-davinci.h>
88 /* SPI Controller registers */
103 /* SPI Controller driver's private data. */
136 if (dspi->rx) { in davinci_spi_rx_buf_u8()
137 u8 *rx = dspi->rx; in davinci_spi_rx_buf_u8()
139 dspi->rx = rx; in davinci_spi_rx_buf_u8()
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| H A D | spi-imx.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
10 #include <linux/dma-mapping.h>
21 #include <linux/spi/spi.h>
26 #include <linux/dma/imx-dma.h>
74 int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi);
93 struct spi_controller *controller; member
133 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
138 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
143 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
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| H A D | spi-pxa2xx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
28 #include <linux/spi/pxa2xx_spi.h>
29 #include <linux/spi/spi.h>
31 #include "spi-pxa2xx.h"
34 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
36 MODULE_ALIAS("platform:pxa2xx-spi");
78 /* LPSS offset from drv_data->ioaddr */
80 /* Register offsets from drv_data->lpss_base or -1 */
104 .reg_capabilities = -1,
114 .reg_capabilities = -1,
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| /openbmc/u-boot/drivers/spi/ |
| H A D | Kconfig | 1 menuconfig SPI config
2 bool "SPI Support"
4 if SPI
7 bool "Enable Driver Model for SPI drivers"
10 Enable driver model for SPI. The SPI slave interface
12 the SPI uclass. Drivers provide methods to access the SPI
14 include/spi.h. The existing spi_slave structure is attached
16 typically use driver-private data instead of extending the
20 bool "SPI memory extension"
22 Enable this option if you want to enable the SPI memory extension.
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | snps,dw-apb-ssi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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| H A D | brcm,spi-bcm-qspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPI controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
17 MSPI : SPI master controller can read and write to a SPI slave device
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| H A D | brcm,bcm63xx-spi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6348/BCM6358 SPI controller
10 - Jonas Gorski <jonas.gorski@gmail.com>
13 Broadcom "Low Speed" SPI controller found in many older MIPS based Broadband
16 This controller has a limitation that can not keep the chip select line active
17 between the SPI transfers within the same SPI message. This can terminate the
18 transaction to some SPI devices prematurely. The issue can be worked around by
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| H A D | samsung,spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/samsung,spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC SPI controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 All the SPI controller nodes should be represented in the aliases node using
14 the following format 'spi{n}' where n is a unique number for the alias.
19 - enum:
20 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
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| H A D | mediatek,spi-mtk-snfi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
14 the Mediatek NAND flash controller. It can perform standard SPI
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
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| H A D | mediatek,spi-mtk-nor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Serial NOR flash controller for MediaTek ARM SoCs
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
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| H A D | mediatek,spi-mt65xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
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| H A D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
12 controller specific like delay in clock or data lines, etc. These properties
13 need to be defined in the peripheral node because they are per-peripheral and
14 there can be multiple peripherals attached to a controller. All those
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| /openbmc/linux/drivers/clk/qcom/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
40 tristate "MSM8916 APCS Clock Controller"
43 Support for the APCS Clock Controller on msm8916 devices. The
49 tristate "MSM8996 CPU Clock Controller"
54 Support for the CPU clock controller on msm8996 devices.
59 tristate "SDX55 and SDX65 APCS Clock Controller"
63 Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
69 tristate "RPM based Clock Controller"
82 tristate "RPM over SMD based Clock Controller"
104 tristate "APQ8084 Global Clock Controller"
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| /openbmc/linux/include/trace/events/ |
| H A D | spi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 #define TRACE_SYSTEM spi
13 TP_PROTO(struct spi_controller *controller),
15 TP_ARGS(controller),
22 __entry->bus_num = controller->bus_num;
25 TP_printk("spi%d", (int)__entry->bus_num)
31 TP_PROTO(struct spi_controller *controller),
33 TP_ARGS(controller)
39 TP_PROTO(struct spi_controller *controller),
41 TP_ARGS(controller)
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| /openbmc/linux/Documentation/spi/ |
| H A D | spi-summary.rst | 2 Overview of Linux kernel SPI support
5 02-Feb-2012
7 What is SPI?
8 ------------
9 The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial
12 standardization body. SPI uses a master/slave configuration.
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
22 SPI masters use a fourth "chip select" line to activate a given SPI slave
24 in parallel. All SPI slaves support chipselects; they are usually active
29 SPI slave functions are usually not interoperable between vendors
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| /openbmc/linux/Documentation/driver-api/mtd/ |
| H A D | spi-nor.rst | 2 SPI NOR framework
5 Part I - Why do we need this framework?
6 ---------------------------------------
8 SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
9 controller operates agnostic of the specific device attached. However, some
10 controllers (such as Freescale's QuadSPI controller) cannot easily handle
11 arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
13 In particular, Freescale's QuadSPI controller must know the NOR commands to
14 find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
15 opcodes, addresses, or data payloads; a SPI controller simply knows to send or
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| /openbmc/linux/include/linux/spi/ |
| H A D | spi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later
21 #include <uapi/linux/spi/spi.h>
33 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
34 * and SPI infrastructure.
39 * struct spi_statistics - statistics for spi transfers
40 * @syncp: seqcount to protect members in this struct for per-cpu update
41 * on 32-bit systems
43 * @messages: number of spi-messages handled
92 u64_stats_update_begin(&__lstats->syncp); \
93 u64_stats_add(&__lstats->field, count); \
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