| /openbmc/u-boot/drivers/sysreset/ |
| H A D | sysreset_mpc83xx.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
31 "e300 Core Data Transaction",
33 "e300 Core Instruction Fetch",
39 "Encryption Core",
62 "TDM-DMAC"
70 "Address-only, Clean Block",
71 "Address-only, lwarx reservation set",
72 "Single-beat or Burst write",
74 "Address-only, Flush Block",
78 "Address-only, sync",
[all …]
|
| /openbmc/linux/Documentation/arch/x86/ |
| H A D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
28 the past a socket always contained a single package (see below), but with the
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - cpuinfo_x86.x86_max_cores:
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/arm/omap/ |
| H A D | ctrl.txt | 11 [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
15 - compatible: Must be one of:
16 "ti,am3-scm"
17 "ti,am4-scm"
18 "ti,dm814-scrm"
19 "ti,dm816-scrm"
20 "ti,omap2-scm"
21 "ti,omap3-scm"
22 "ti,omap4-scm-core"
23 "ti,omap4-scm-padconf-core"
[all …]
|
| /openbmc/linux/drivers/remoteproc/ |
| H A D | ti_k3_r5_remoteproc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
9 #include <linux/dma-mapping.h>
19 #include <linux/omap-mailbox.h>
33 /* R5 TI-SCI Processor Configuration Flags */
47 /* R5 TI-SCI Processor Control Flags */
50 /* R5 TI-SCI Processor Status Flags */
59 * struct k3_r5_mem - internal memory structure
77 * Single-CPU mode : AM64x SoCs only
[all …]
|
| H A D | xlnx_r5_remoteproc.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
30 * reflects possible values of xlnx,cluster-mode dt-property
34 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
39 * struct mem_bank_data - Memory Bank description
43 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
76 * accepted for system-dt specifications and upstreamed in linux kernel
[all …]
|
| /openbmc/u-boot/doc/device-tree-bindings/adc/ |
| H A D | st,stm32-adc.txt | 3 STM32 ADC is a successive approximation analog-to-digital converter.
5 in single, continuous, scan or discontinuous mode. Result of the ADC is
6 stored in a left-aligned or right-aligned 32-bit data register.
10 voltage goes beyond the user-defined, higher or lower thresholds.
16 - regular conversion can be done in sequence, running in background
17 - injected conversions have higher priority, and so have the ability to
22 -----------------------------------
24 - compatible: Should be one of:
25 "st,stm32f4-adc-core"
26 "st,stm32h7-adc-core"
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/ |
| H A D | example-schema.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 # All the top-level keys are standard json-schema keywords except for
10 $id: http://devicetree.org/schemas/example-schema.yaml#
11 # $schema is the meta-schema this schema should be validated with.
12 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Rob Herring <robh@kernel.org>
20 A more detailed multi-line description of the binding.
44 - items:
51 - enum:
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | cache.json | 105 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
108 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
111 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
114 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
117 …This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache",
120 … This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache"
123 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
126 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
129 …ta cache entering write streaming mode.This event counts for each entry into write-streaming mode",
132 …ata cache entering write streaming mode.This event counts for each entry into write-streaming mode"
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | st,stm32-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
12 in single, continuous, scan or discontinuous mode. Result of the ADC is
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
[all …]
|
| H A D | xilinx-xadc.txt | 16 communication. Xilinx provides a standard IP core that can be used to access the
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
28 Xilinx System Management Wizard fabric IP core to access the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
32 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | cache.json | 102 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L…
105 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L…
114 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami…
117 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami…
126 …ta cache write streaming mode. This event counts for each cycle where the core is in write streami…
129 …ta cache write streaming mode. This event counts for each cycle where the core is in write streami…
132 …L3 cache write streaming mode. This event counts for each cycle where the core is in write streami…
135 …L3 cache write streaming mode. This event counts for each cycle where the core is in write streami…
138 …el cache write streaming mode. This event counts for each cycle where the core is in write streami…
141 …el cache write streaming mode. This event counts for each cycle where the core is in write streami…
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | pistachio-clock.txt | 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
18 ----------------------
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | other.json | 3 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
6 …Core cycles where the core was running with power-delivery for baseline license level 0. This inc…
11 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
14 …Core cycles where the core was running with power-delivery for license level 1. This includes hig…
19 …"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped…
22 …Core cycles where the core was running with power-delivery for license level 2 (introduced in Skyl…
30 …core's cache, after the data is forwarded back to the requestor and indicating the data was found …
38 …core's caches, after the data is forwarded back to the requestor, and indicating the data was foun…
46 …core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Ex…
54 … was not found (IHitI) in this core's caches. A single snoop response from the core counts on all …
[all …]
|
| /openbmc/linux/drivers/staging/media/atomisp/ |
| H A D | notes.txt | 6 The ISP has its own address-space and main memory needs to be mapped into
11 the hmm code finds the backing hmm-buffer-object (hmm_bo) by looking
25 So in this case a single binary handles the entire pipeline.
29 on the ISP can do multiple processing steps in a single pipeline
30 element (in a single binary).
36 the core atomisp code. The most important parts of the struct
37 are filled by the atomisp core itself, like e.g. the port number.
40 -metadata_width, metadata_height, metadata_effective_width, set by
41 the ov5693 driver (and used by the atomisp core)
42 -raw_bayer_order, adjusted by the ov2680 driver when flipping since
|
| /openbmc/u-boot/board/intel/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
15 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
23 mini-ITX form factor containing the Intel Braswell SoC, which has
24 a 64-bit quad-core, single-thread, Intel Atom processor, along with
25 serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
48 This is the Intel Edison Compute Module. It contains a dual core Intel
50 eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
56 Arduino-certified development and prototyping boards based on Intel
57 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
58 single-core, single-thread, Intel Pentium processor instrunction set
[all …]
|
| /openbmc/docs/designs/mctp/ |
| H A D | mctp-userspace.md | 14 The MCTP core specification just provides the packetisation, routing and
20 provides a socket-based interface for other processes to send and receive
24 handling local MCTP-stack configuration, like local EID assignments.
28 1. the core MCTP stack
30 2. one or more binding implementations (eg, MCTP-over-serial), which interact
33 3. an interface to handler applications over a unix-domain socket.
38 - an "upper" messaging transmit/receive interface, for tx/rx of a full message
41 - a "lower" hardware binding for transmit/receive of individual packets,
42 providing a method for the core to tx/rx each packet to hardware, and defines
45 The lower interface would be plugged in to one of a number of hardware-specific
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
24 AM62 SoC family support a single R5F core only which runs Device Manager
[all …]
|
| H A D | xlnx,zynqmp-r5fss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
[all …]
|
| /openbmc/linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
32 A physical connector on the motherboard that accepts a single memory
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
45 same branch can be used in single mode or in lockstep mode. When
50 of correcting more errors than on single mode.
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| H A D | cache.json | 111 … prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache",
114 …o prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache"
117 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
120 …core is configured with a per-core L2 cache: This event does not count. +//0 If the core is config…
123 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
126 …unted, regardless of whether they allocate. If either the core is configured without a per-core L2…
141 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
144 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
147 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
150 …he write streaming mode. This event counts for each cycle where the core is in write-streaming mod…
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/cpu/ |
| H A D | cpu-topology.txt | 6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
17 The bottom hierarchy level sits at core or thread level depending on whether
18 symmetric multi-threading (SMT) is supported or not.
23 in the system and map to the hierarchy level "core" above.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | apple,aic2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/i2c/ |
| H A D | i2c.txt | 8 -----------------------------
10 - #address-cells - should be <1>. Read more about addresses below.
11 - #size-cells - should be <0>.
12 - compatible - name of I2C bus controller
18 are described by a single value.
21 -----------------------------
26 - clock-frequency
29 - i2c-bus
31 devices and non-I2C devices, the 'i2c-bus' subnode can be used for
32 populating I2C devices. If the 'i2c-bus' subnode is present, only
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | ite,it66121.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Phong LE <ple@baylibre.com>
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The IT66121 is a high-performance and low-power single channel HDMI
21 - ite,it66121
22 - ite,it6610
27 reset-gpios:
31 vrf12-supply:
[all …]
|
| /openbmc/linux/drivers/hwspinlock/ |
| H A D | hwspinlock_internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
7 * Contact: Ohad Ben-Cohen <ohad@wizery.com>
19 * struct hwspinlock_ops - platform-specific hwspinlock handlers
21 * @trylock: make a single attempt to take the lock. returns 0 on
24 * @bust: optional, platform-specific bust handler, called by hwspinlock
25 * core to bust a specific lock.
26 * @relax: optional, platform-specific relax handler, called by hwspinlock
27 * core while spinning on a lock, between two successive
38 * struct hwspinlock - this struct represents a single hwspinlock instance
[all …]
|