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/openbmc/linux/Documentation/devicetree/bindings/sifive/
H A Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
16 Until these IP blocks (or IP integration) support version
17 auto-discovery, the maintainers of these IP blocks intend to increment
19 interface to these IP blocks changes, or when the functionality of the
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/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 SiFive, Inc.
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
18 achievable period. PWM RTL that corresponds to the IP block version
19 numbers can be found here -
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: spi-controller.yaml#
20 - enum:
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive Core Local Interruptor
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
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/openbmc/
Dopengrok1.0.log1 2025-03-28 03:00:39.864-0500 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-03-28 03:00:39.984-0500 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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Dopengrok2.0.log1 2025-03-27 03:00:39.486-0500 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-03-27 03:00:39.605-0500 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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