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/openbmc/linux/arch/arm/mach-lpc32xx/
H A Dsuspend.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-lpc32xx/suspend.S
39 stmfd r0!, {r3 - r7, sp, lr}
63 @ Setup self-refresh with support for manual exit of
64 @ self-refresh mode
70 @ Wait for self-refresh acknowledge, clocks to the DRAM device
71 @ will automatically stop on start of self-refresh
76 bne 3b @ Branch until self-refresh mode starts
78 @ Enter direct-run mode from run mode
113 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
[all …]
H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-lpc32xx/pm.c
15 * direct-run, and halt modes. When switching between halt and run modes,
16 * the CPU transistions through direct-run mode. For Linux, direct-run
25 * Direct-run mode:
36 * wake the system up back into direct-run mode.
38 * DRAM refresh
39 * DRAM clocking and refresh are slightly different for systems with DDR
41 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
42 * a transition to direct-run mode will stop all DDR accesses (no clocks).
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
28 - const: dmc_clk
[all …]
/openbmc/linux/include/soc/at91/
H A Dsama7-ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
44 #define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
45 #define DDR3PHY_ZQ0SR0_PUO_OFF (5) /* Pull-up output impedance select offset */
46 #define DDR3PHY_ZQ0SR0_PDODT_OFF (10) /* Pull-down on-die termination impedance select offset */
47 #define DDR3PHY_ZQ0SRO_PUODT_OFF (15) /* Pull-up on-die termination impedance select offset */
55 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
56 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PH…
57 …ELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic…
58 …TAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-r…
59 #define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */
[all …]
H A Dat91sam9_sdramc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
27 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
54 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
57 #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
62 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
63 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
74 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
H A Dat91sam9_ddrsdr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 #define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
22 #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
59 #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
74 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
81 #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
[all …]
/openbmc/linux/drivers/gpu/drm/
H A Ddrm_self_refresh_helper.c1 // SPDX-License-Identifier: MIT
27 * framework to implement panel self refresh (SR) support. Drivers are
31 * &drm_connector_state.self_refresh_aware to true at runtime if it is SR-aware
32 * (meaning it knows how to initiate self refresh on the panel).
38 * that tells you to disable/enable SR on the panel instead of power-cycling it.
72 struct drm_crtc *crtc = sr_data->crtc; in drm_self_refresh_helper_entry_work()
73 struct drm_device *dev = crtc->dev; in drm_self_refresh_helper_entry_work()
85 ret = -ENOMEM; in drm_self_refresh_helper_entry_work()
90 state->acquire_ctx = &ctx; in drm_self_refresh_helper_entry_work()
98 if (!crtc_state->enable) in drm_self_refresh_helper_entry_work()
[all …]
/openbmc/linux/arch/arm/mach-socfpga/
H A Dself-refresh.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
32 .arch armv7-a
44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
125 .word . - socfpga_sdram_self_refresh
/openbmc/linux/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/
H A Dali_drw.json24 "BriefDescription": "A Read-Modify-Write Op at HIF interface. The unit is 64B.",
136 "BriefDescription": "A read-write turnaround.",
150 "BriefDescription": "A Write-After-Read hazard.",
157 "BriefDescription": "A Read-After-Write hazard.",
164 "BriefDescription": "A Write-After-Write hazard.",
171 "BriefDescription": "Rank0 enters self-refresh(SRE).",
178 "BriefDescription": "Rank1 enters self-refresh(SRE).",
185 "BriefDescription": "Rank2 enters self-refresh(SRE).",
192 "BriefDescription": "Rank3 enters self-refresh(SRE).",
199 "BriefDescription": "Rank0 enters power-down(PDE).",
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt3 - compatible: "rockchip,rk3288-dmc", "syscon"
4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,grf: this driver should access grf regs, so need get grf here
6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8 - rockchip,noc: this driver should access noc regs, so need get noc here
9 - reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
10 - clock: must include clock specifiers corresponding to entries in the clock-names property.
11 - clock-output-names: from common clock binding to override the default output clock name
18 -logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-su…
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dsleep.S2 * Low-level PXA250/210 sleep/wakeUp support
17 #include "pxa2xx-regs.h"
28 * pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
55 @ prepare SDRAM refresh settings
59 @ enable SDRAM self-refresh mode
62 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
96 @ prepare SDRAM refresh settings
100 @ enable SDRAM self-refresh mode
107 @ We keep the change-down close to the actual suspend on SDRAM
108 @ as possible to eliminate messing about with the refresh clock
[all …]
/openbmc/linux/drivers/cpuidle/
H A Dcpuidle-zynq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013 Xilinx
7 * based on arch/arm/mach-at91/cpuidle.c
9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
10 * to implement two idle states -
11 * #1 wait-for-interrupt
12 * #2 wait-for-interrupt and RAM self refresh
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
61 .name = "cpuidle-zynq",
H A Dcpuidle-at91.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * based on arch/arm/mach-kirkwood/cpuidle.c
7 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
8 * to implement two idle states -
9 * #1 wait-for-interrupt
10 * #2 wait-for-interrupt and RAM self refresh
43 .desc = "WFI and DDR Self Refresh",
51 at91_standby = (void *)(dev->dev.platform_data); in at91_cpuidle_probe()
58 .name = "cpuidle-at91",
H A Dcpuidle-kirkwood.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * The cpu idle uses wait-for-interrupt and DDR self refresh in order
6 * to implement two idle states -
7 * #1 wait-for-interrupt
8 * #2 wait-for-interrupt and DDR self refresh
47 .desc = "WFI and DDR Self Refresh",
81 MODULE_ALIAS("platform:kirkwood-cpuidle");
/openbmc/linux/arch/sh/boards/mach-kfr2r09/
H A Dsdram.S1 /* SPDX-License-Identifier: GPL-2.0
3 * KFR2R09 sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
/openbmc/linux/arch/sh/boards/mach-migor/
H A Dsdram.S1 /* SPDX-License-Identifier: GPL-2.0
3 * Migo-R sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
51 mov #-1, r4
/openbmc/linux/arch/sh/boards/mach-ap325rxa/
H A Dsdram.S1 /* SPDX-License-Identifier: GPL-2.0
3 * AP325RXA sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* SBSC: disable power down and put in self-refresh mode */
42 /* SBSC: set auto-refresh mode */
51 mov #-1, r4
/openbmc/u-boot/tools/dtoc/
H A Dfdt.py2 # SPDX-License-Identifier: GPL-2.0+
17 # contains the base classes and defines the high-level API. You can use
40 def __init__(self, node, offset, name, bytes): argument
41 self._node = node
42 self._offset = offset
43 self.name = name
44 self.value = None
45 self.bytes = str(bytes)
46 self.dirty = False
48 self.type = TYPE_BOOL
[all …]
/openbmc/linux/arch/sh/boards/mach-ecovec24/
H A Dsdram.S1 /* SPDX-License-Identifier: GPL-2.0
3 * Ecovec24 sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
41 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
/openbmc/linux/arch/sh/kernel/cpu/shmobile/
H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0
28 * Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
29 * Standby Self-Refresh mode is above plus stopped clocks
37 * U-standby mode is unsupported since it needs bootloader hacks
62 /* Let assembly snippet in on-chip memory handle the rest */ in sh_mobile_call_standby()
88 sdp->addr.stbcr = 0xa4150020; /* STBCR */ in sh_mobile_register_self_refresh()
89 sdp->addr.bar = 0xa4150040; /* BAR */ in sh_mobile_register_self_refresh()
90 sdp->addr.pteh = 0xff000000; /* PTEH */ in sh_mobile_register_self_refresh()
91 sdp->addr.ptel = 0xff000004; /* PTEL */ in sh_mobile_register_self_refresh()
92 sdp->addr.ttb = 0xff000008; /* TTB */ in sh_mobile_register_self_refresh()
[all …]
/openbmc/linux/arch/arm/mach-at91/
H A Dpm_suspend.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-at91/pm_slow_clock.S
13 #include "pm_data-offsets.h"
16 .arch armv7-a
92 * @ena: 0 - disable regulator
93 * 1 - enable regulator
125 * Enable self-refresh
164 /* Switch to self-refresh. */
170 /* Wait for self-refresh enter. */
176 /* Disable DX DLLs for non-backup modes. */
[all …]
/openbmc/linux/arch/sh/boards/mach-se/7724/
H A Dsdram.S1 /* SPDX-License-Identifier: GPL-2.0
3 * MS7724SE sdram self/auto-refresh setup code
11 #include <asm/asm-offsets.h>
13 #include <asm/romimage-macros.h>
15 /* code to enter and leave self-refresh. must be self-contained.
16 * this code will be copied to on-chip memory and executed from there.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
72 /* DBSC: re-initialize and put in auto-refresh */
/openbmc/openbmc/poky/bitbake/lib/bb/ui/
H A Dtaskexp_ncurses.py2 # BitBake Graphical ncurses-based Dependency Explorer
7 # Copyright (C) 2007 - 2008 Richard Purdie
8 # Copyright (C) 2022 - 2024 David Reyna
10 # SPDX-License-Identifier: GPL-2.0-only
15 # $ bitbake -g -u taskexp_ncurses zlib acl
17 # Self-test example (executes a script of GUI actions):
18 # $ TASK_EXP_UNIT_TEST=1 bitbake -g -u taskexp_ncurses zlib acl
22 # $ TASK_EXP_UNIT_TEST=1 bitbake -g -u taskexp_ncurses zlib acl foo
28 # Self-test with no terminal example (only tests dependency fetch from bitbake):
29 # $ TASK_EXP_UNIT_TEST_NOTERM=1 bitbake -g -u taskexp_ncurses quilt
[all …]
/openbmc/openbmc/poky/bitbake/lib/toaster/tests/browser/
H A Dtest_layerdetails_page.py5 # SPDX-License-Identifier: GPL-2.0-only
7 # Copyright (C) 2013-2016 Intel Corporation
25 def __init__(self, *args, **kwargs): argument
26 super(TestLayerDetailsPage, self).__init__(*args, **kwargs)
28 self.initial_values = None
29 self.url = None
30 self.imported_layer_version = None
32 def setUp(self): argument
39 self.project = Project.objects.create(name='foo', release=release)
41 name = "meta-imported"
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dsuspend-imx53.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
60 /* Set FDVFS bit of M4IF_MCR0 to request DDR to enter self-refresh */
66 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to enter self-refresh */
115 /* Clear FDVFS bit of M4IF_MCR0 to request DDR to exit self-refresh */
121 /* Poll FDVACK bit of M4IF_MCR to wait for DDR to exit self-refresh */
134 .word . - imx53_suspend

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