| /openbmc/qemu/include/hw/arm/ |
| H A D | armv7m.h | 20 #define TYPE_BITBAND "ARM-bitband-memory"
44 * + Property "cpu-type": CPU type to instantiate
45 * + Property "num-irq": number of external IRQ lines
46 * + Property "num-prio-bits": number of priority bits in the NVIC
48 * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
51 * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)
52 * + Property "init-nsvtor": non-secure VTOR reset value (forwarded to CPU object)
55 * + Property "enable-bitband": expose bitbanded IO
56 * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
57 * to CPU object pmsav7-dregion property; default is whatever the default
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| H A D | xlnx-zynqmp.h | 24 #include "hw/net/xlnx-zynqmp-can.h"
25 #include "hw/ide/ahci-sysbus.h"
29 #include "hw/dma/xlnx-zdma.h"
31 #include "hw/intc/xlnx-zynqmp-ipi.h"
32 #include "hw/rtc/xlnx-zynqmp-rtc.h"
38 #include "hw/nvram/xlnx-bbram.h"
39 #include "hw/nvram/xlnx-zynqmp-efuse.h"
40 #include "hw/or-irq.h"
41 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
42 #include "hw/misc/xlnx-zynqmp-crf.h"
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| H A D | virt.h | 22 * + we want to present a very stripped-down minimalist platform,
47 /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
85 /* indices of IO regions located after the RAM */
146 bool secure; member
198 if (vms->gic_version == VIRT_GIC_VERSION_3) { in virt_redist_capacity()
203 return vms->memmap[region].size / redist_size; in virt_redist_capacity()
206 /* Return the number of used redistributor regions */
211 assert(vms->gic_version != VIRT_GIC_VERSION_2); in virt_gicv3_redist_region_count()
213 return (MACHINE(vms)->smp.cpus > redist0_capacity && in virt_gicv3_redist_region_count()
214 vms->highmem_redists) ? 2 : 1; in virt_gicv3_redist_region_count()
|
| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
31 2/ The ECC engine is part of the NAND part (on-die), in this
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| /openbmc/qemu/hw/arm/ |
| H A D | armv7m.c | 4 * Copyright (c) 2006-2007 CodeSourcery.
16 #include "hw/qdev-properties.h"
17 #include "hw/qdev-clock.h"
20 #include "qemu/error-report.h"
25 #include "target/arm/cpu-features.h"
26 #include "target/arm/cpu-qom.h"
34 return s->base | (offset & 0x1ffffff) >> 5; in bitband_addr()
49 addr = bitband_addr(s, offset) & (-size); in bitband_read()
50 res = address_space_read(&s->source_as, addr, attrs, buf, size); in bitband_read()
55 bitpos = (offset >> 2) & ((size * 8) - 1); in bitband_read()
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| H A D | virt.c | 2 * ARM mach-virt emulation
23 * + we want to present a very stripped-down minimalist platform,
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
56 #include "qemu/error-report.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | omap_sec_common.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
14 * Invoke secure ROM API on high-security (HS) device variants. It formats
16 * triggering the actual low-level smc entry.
21 * Invoke a secure ROM API on high-secure (HS) device variants that can be used
22 * to verify a secure blob by authenticating and optionally decrypting it. The
24 * into the blob during the signing/encryption step when the secure blob was
30 * Return the start of secure reserved RAM, if a default start address has
36 * Invoke a secure HAL API that allows configuration of the external memory
37 * firewall regions.
44 * Invoke a secure HAL API on high-secure (HS) device variants that reserves a
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| /openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/svc/rm/ |
| H A D | api.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
21 #define SC_RM_MR_ALL ((sc_rm_mr_t)UINT8_MAX) /* All memory regions */
26 #define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */
27 #define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */
31 #define SC_RM_PERM_SEC_R 1U /* Secure RO */
32 #define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */
33 #define SC_RM_PERM_SEC_RW 3U /* Secure R/W */
34 #define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */
35 #define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */
36 #define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */
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| /openbmc/linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | ti,secure-proxy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,secure-proxy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments' Secure Proxy
10 - Nishanth Menon <nm@ti.com>
13 The Texas Instruments' secure proxy is a mailbox controller that has
15 Message manager is broken up into different address regions that are
16 called "threads" or "proxies" - each instance is unidirectional and is
22 pattern: "^mailbox@[0-9a-f]+$"
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| /openbmc/linux/Documentation/networking/devlink/ |
| H A D | iosm.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 The ``iosm`` driver implements the following driver-specific parameters.
15 .. list-table:: Driver-specific parameters implemented
18 * - Name
19 - Type
20 - Mode
21 - Description
22 * - ``erase_full_flash``
23 - u8
24 - runtime
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| /openbmc/u-boot/doc/ |
| H A D | README.fsl-trustzone-components | 2 TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone
6 is left to a root-of-trust security software layer (running in EL3
12 TZPC-BP147 (TrustZone Protection Controller)
14 - Depends on CONFIG_FSL_TZPC_BP147 configuration flag.
15 - Separates Secure World and Normal World on-chip RAM (OCRAM) spaces.
16 - Provides a programming model to set access control policy via the TZPC
19 TZASC-400 (TrustZone Address Space Controller)
21 - Depends on CONFIG_FSL_TZASC_400 configuration flag.
22 - Separates Secure World and Normal World external memory spaces for bus masters
23 such as processors and DMA-equipped peripherals.
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| /openbmc/qemu/include/hw/misc/ |
| H A D | tz-ppc.h | 13 * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
15 * https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
17 * The PPC sits in front of peripherals and allows secure software to
22 * The PPC has no register interface -- it is configured purely by a
24 * they are either hardwired or exposed in an ad-hoc register interface by
36 * we provide 16 MMIO regions, one per port, and the user maps these into
40 * + sysbus MMIO regions 0..15: MemoryRegions defining the upstream end
46 * port N's upstream is always sysbus MMIO region N. Dummy regions should
53 * accessible to non-privileged transactions
58 * + Named GPIO output "irq": set for a transaction-failed interrupt
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| /openbmc/qemu/docs/system/i386/ |
| H A D | amd-memory-encryption.rst | 1 AMD Secure Encrypted Virtualization (SEV)
4 Secure Encrypted Virtualization (SEV) is a feature found on AMD processors.
6 SEV is an extension to the AMD-V architecture which supports running encrypted
15 AMD secure processor (AMD-SP), which is present in AMD SOCs. Firmware running
16 inside the AMD-SP provides commands to support a common VM lifecycle. This
21 Secure Encrypted Virtualization - Encrypted State (SEV-ES) builds on the SEV
28 Launching (SEV and SEV-ES)
29 --------------------------
38 For a SEV-ES guest, the ``LAUNCH_UPDATE_VMSA`` command is also used to encrypt the
43 its public Diffie-Hellman key (PDH) and session parameters. These inputs
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| /openbmc/linux/drivers/nvdimm/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "NVDIMM (Non-Volatile Memory Device) Support"
9 Generic support for non-volatile memory devices including
10 ACPI-6-NFIT defined resources. On platforms that define an
28 non-standard OEM-specific E820 memory type (type-12, see
31 Documentation/admin-guide/kernel-parameters.rst). This driver converts
33 capable of DAX (direct-access) file system mappings. See
34 Documentation/driver-api/nvdimm/nvdimm.rst for more details.
69 management sub-system. By default persistent memory does
85 sub-divide a namespace into character devices that can only be
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| /openbmc/qemu/include/hw/intc/ |
| H A D | arm_gicv3_common.h | 37 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
48 /* Number of SGI target-list bits */
55 * For some distributor fields we want to model the array of 32-bit
80 /* Return a pointer to the 32-bit word containing the specified bit. */
90 * Group0, Group1 (Secure) and Group1 (NonSecure)
92 * In the state struct they are implemented as a 3-element array which
99 * must be prepared to cope with a Group 1 Secure interrupt even if it does
102 * treat an incoming Group 1 Secure interrupt as if it were Group 0.
104 * in a no-EL3 CPU: we would otherwise have to translate back and forth
112 * group-related, so those indices are just 0 for S and 1 for NS.
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| /openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/ |
| H A D | 0012-Platform-CS1000-Increase-BL2-partition-size.patch | 6 Enabling secure debug increases the BL2 code size considerably. This
7 patch increases the BL2 partition size to enable secure debug feature
8 on Corstone-1000. The TF-M partition size has to be decreased for this.
12 Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
13 Signed-off-by: Bence Balogh <bence.balogh@arm.com>
14 Upstream-Status: Backport [https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/30406]
15 ---
16 .../ext/target/arm/corstone1000/CMakeLists.txt | 9 ++++++---
17 .../target/arm/corstone1000/create-flash-image.sh | 14 ++++++++------
18 .../arm/corstone1000/partition/flash_layout.h | 4 ++--
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| /openbmc/linux/Documentation/devicetree/bindings/sram/ |
| H A D | sram.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
13 Simple IO memory regions to be managed by the genalloc API.
19 Following the generic-names recommended practice, node names should
30 - mmio-sram
31 - amlogic,meson-gxbb-sram
32 - arm,juno-sram-ns
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| /openbmc/qemu/docs/system/arm/ |
| H A D | virt.rst | 8 idiosyncrasies and limitations of a particular bit of real-world
16 ``virt-5.0`` machine type will behave like the ``virt`` machine from
17 the QEMU 5.0 release, and migration should work between ``virt-5.0``
18 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
20 the non-versioned ``virt`` machine type.
27 - PCI/PCIe devices
28 - Flash memory
29 - Either one or two PL011 UARTs for the NonSecure World
30 - An RTC
31 - The fw_cfg device that allows a guest to obtain data from QEMU
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| /openbmc/u-boot/arch/arm/mach-omap2/ |
| H A D | sec-common.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * (C) Copyright 2016-2017
9 * Daniel Allred <d-allred@ti.com>
23 #include <asm/ti-common/sys_proto.h>
35 /* Index for signature PPA-based TI HAL APIs */
99 while (--image_end > image) { in find_sig_start()
101 ch = image_end - magic_str_len + 1; in find_sig_start()
129 *size = sig_addr - cert_addr; /* Subtract out the signature size */ in secure_boot_verify_image()
132 *size -= ((u32 *)*image)[HEADER_SIZE_OFFSET]; in secure_boot_verify_image()
135 /* Check if image load address is 32-bit aligned */ in secure_boot_verify_image()
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/ |
| H A D | Memory.v1_20_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
64 "description": "The available OEM-specific actions for this resource.",
65 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
105 … "longDescription": "This type shall contain CXL-specific properties for a memory device.",
107 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
130 …"description": "Total device non-volatile memory capacity in MiB staged for next activation. The …
131 …escription": "The value of this property shall indicate the total device non-volatile memory capac…
167 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
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| /openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/ |
| H A D | Memory.v1_20_0.json | 4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
64 "description": "The available OEM-specific actions for this resource.",
65 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
105 … "longDescription": "This type shall contain CXL-specific properties for a memory device.",
107 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
130 …"description": "Total device non-volatile memory capacity in MiB staged for next activation. The …
131 …escription": "The value of this property shall indicate the total device non-volatile memory capac…
167 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
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| /openbmc/linux/drivers/soc/qcom/ |
| H A D | ocmem.c | 1 // SPDX-License-Identifier: GPL-2.0-only
63 struct ocmem_region *regions; member
103 writel(data, ocmem->mmio + reg); in ocmem_write()
108 return readl(ocmem->mmio + reg); in ocmem_read()
117 for (i = 0; i < ocmem->config->num_regions; i++) { in update_ocmem()
118 struct ocmem_region *region = &ocmem->regions[i]; in update_ocmem()
120 if (region->mode == THIN_MODE) in update_ocmem()
124 dev_dbg(ocmem->dev, "ocmem_region_mode_control %x\n", in update_ocmem()
129 for (i = 0; i < ocmem->config->num_regions; i++) { in update_ocmem()
130 struct ocmem_region *region = &ocmem->regions[i]; in update_ocmem()
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| /openbmc/qemu/target/arm/ |
| H A D | ptw.c | 6 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "qemu/main-loop.h"
13 #include "exec/exec-all.h"
14 #include "exec/page-protection.h"
17 #include "cpu-features.h"
20 # include "tcg/oversized-guest.h"
33 * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
40 * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
46 * - if the in_ptw_idx is an ARMMMUIdx_Phys_* then the mmuidx
48 * - if the in_ptw_idx is an ARMMMUIdx_Stage2* then the security
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-gic-v3.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
24 #include <linux/irqchip/arm-gic-common.h>
25 #include <linux/irqchip/arm-gic-v3.h>
26 #include <linux/irqchip/irq-partition-percpu.h>
29 #include <linux/arm-smccc.h>
36 #include "irq-gic-common.h"
83 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
87 * When security is enabled, non-secure priority values from the (re)distributor
91 * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure
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| /openbmc/linux/Documentation/admin-guide/ |
| H A D | thunderbolt.rst | 1 .. SPDX-License-Identifier: GPL-2.0
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
35 ``/etc/udev/rules.d/99-local.rules``::
66 secure
68 addition to UUID the device (if it supports secure connect) is sent
92 If the security level reads as ``user`` or ``secure`` the connected
101 Authorizing devices when security level is ``user`` or ``secure``
102 -----------------------------------------------------------------
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|