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/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-ast2600-evb.dts46 vcc_sdhci0: regulator-vcc-sdhci0 {
48 regulator-name = "SDHCI0 Vcc";
55 vccq_sdhci0: regulator-vccq-sdhci0 {
57 regulator-name = "SDHCI0 VccQ";
299 * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be
302 * power load switch that provides 3.3v to sdhci0 vdd, GPIOV1 is connected to
304 * sdhci0 bus.
305 * If GPIOV0 is active high, sdhci0 is enabled, otherwise, sdhci0 is disabled.
306 * If GPIOV1 is active high, 3.3v power load switch is enabled, sdhci0 signal
308 * sdhci0 signal voltage becomes 1.8v.
[all …]
H A Daspeed-ast2600-evb-a1.dts10 /delete-node/regulator-vcc-sdhci0;
12 /delete-node/regulator-vccq-sdhci0;
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-mini-emmc0.dts20 mmc0 = &sdhci0;
50 sdhci0: sdhci@ff160000 { label
66 &sdhci0 {
H A Dzynq-microzed.dts17 mmc0 = &sdhci0;
60 &sdhci0 {
H A Dzynq-zybo.dts17 mmc0 = &sdhci0;
57 &sdhci0 {
H A Dzynq-syzygy-hub.dts18 mmc0 = &sdhci0;
63 &sdhci0 {
H A Dbitmain-antminer-s9.dts18 mmc0 = &sdhci0;
64 &sdhci0 {
H A Dzynq-zybo-z7.dts18 mmc0 = &sdhci0;
67 &sdhci0 {
H A Dversal-mini-emmc0.dts38 sdhci0: sdhci@f1040000 { label
53 mmc0 = &sdhci0;
H A Dzynq-zed.dts17 mmc0 = &sdhci0;
63 &sdhci0 {
H A Dzynqmp-zc1751-xm019-dc5.dts24 mmc0 = &sdhci0;
93 &sdhci0 {
H A Dzynq-topic-miami.dts19 mmc0 = &sdhci0;
84 &sdhci0 {
H A Dzynq-dlc20-rev1.0.dts20 mmc0 = &sdhci0;
83 &sdhci0 {
H A Dzynq-zturn.dts23 mmc0 = &sdhci0;
82 &sdhci0 {
H A Dzynq-zc706.dts18 mmc0 = &sdhci0;
219 pinctrl_sdhci0_default: sdhci0-default {
312 &sdhci0 {
H A Dzynq-zc702.dts18 mmc0 = &sdhci0;
314 pinctrl_sdhci0_default: sdhci0-default {
407 &sdhci0 {
H A Dzynqmp-zc1751-xm015-dc1.dts23 mmc0 = &sdhci0;
148 &sdhci0 {
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zybo.dts16 mmc0 = &sdhci0;
51 &sdhci0 {
H A Dzynq-zed.dts16 mmc0 = &sdhci0;
50 &sdhci0 {
H A Dzynq-zturn-common.dtsi22 mmc0 = &sdhci0;
75 &sdhci0 {
H A Dzynq-ebaz4205.dts78 pinctrl_sdhci0_default: sdhci0-default {
133 &sdhci0 {
H A Dzynq-zc706.dts17 mmc0 = &sdhci0;
218 pinctrl_sdhci0_default: sdhci0-default {
306 &sdhci0 {
H A Dzynq-zc702.dts18 mmc0 = &sdhci0;
318 pinctrl_sdhci0_default: sdhci0-default {
406 &sdhci0 {
/openbmc/u-boot/arch/arm/mach-zynqmp/
H A DKconfig109 SDHCI0 controller. Platforms which have only one SDHCI controller
110 shouldn't enable this option because it for software SDHCI0 or SDHCI1
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm019-dc5.dts26 mmc0 = &sdhci0;
249 pinctrl_sdhci0_default: sdhci0-default {
405 &sdhci0 {

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