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/openbmc/linux/drivers/platform/x86/
H A Dintel_scu_ipc.c3 * Driver for the Intel SCU IPC mechanism
8 * SCU running in ARC processor communicates with other entity running in IA
9 * core through IPC mechanism which in turn messaging between IA core ad SCU.
10 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
11 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
40 * To read or write information to the SCU, driver writes to IPC-1 memory
47 * the IPC-1 register block, causing an interrupt to the SCU
49 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
73 * 16 byte buffer for sending and receiving data to and from SCU.
82 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
[all …]
H A Dintel_scu_ipcutil.c3 * Driver for the Intel SCU IPC mechanism
8 * This driver provides IOCTL interfaces to call Intel SCU IPC driver API.
25 struct intel_scu_ipc_dev *scu; variable
45 * Allow the user to perform register accesses on the SCU via the
58 return intel_scu_ipc_dev_readv(scu, data->addr, data->data, count); in scu_reg_access()
60 return intel_scu_ipc_dev_writev(scu, data->addr, data->data, count); in scu_reg_access()
62 return intel_scu_ipc_dev_update(scu, data->addr[0], data->data[0], in scu_reg_access()
70 * scu_ipc_ioctl - control ioctls for the SCU
71 * @fp: file handle of the SCU device
75 * Support the I/O and firmware flashing interfaces of the SCU
[all …]
H A Dintel_scu_pltdrv.c3 * Platform driver for the Intel SCU.
23 struct intel_scu_ipc_dev *scu; in intel_scu_platform_probe() local
33 scu = devm_intel_scu_ipc_register(&pdev->dev, &scu_data); in intel_scu_platform_probe()
34 if (IS_ERR(scu)) in intel_scu_platform_probe()
35 return PTR_ERR(scu); in intel_scu_platform_probe()
37 platform_set_drvdata(pdev, scu); in intel_scu_platform_probe()
59 MODULE_DESCRIPTION("Intel SCU platform driver");
/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2600.c19 * SCU 80 & 90 clock stop control for MAC controllers
87 * SCU 320 & 330 Frequency counters
216 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) in ast2600_get_pll_rate() argument
224 pll_reg = readl(&scu->h_pll_param); in ast2600_get_pll_rate()
227 pll_reg = readl(&scu->m_pll_param); in ast2600_get_pll_rate()
230 pll_reg = readl(&scu->d_pll_param); in ast2600_get_pll_rate()
233 pll_reg = readl(&scu->e_pll_param); in ast2600_get_pll_rate()
254 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); in ast2600_get_pll_rate()
271 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) in ast2600_get_apll_rate() argument
273 u32 hw_rev = readl(&scu->chip_id1); in ast2600_get_apll_rate()
[all …]
H A Dclk_ast2500.c52 extern u32 ast2500_get_clkin(struct ast2500_scu *scu) in ast2500_get_clkin() argument
54 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ in ast2500_get_clkin()
62 extern u32 ast2500_get_mpll_rate(struct ast2500_scu *scu) in ast2500_get_mpll_rate() argument
64 u32 clkin = ast2500_get_clkin(scu); in ast2500_get_mpll_rate()
65 u32 mpll_reg = readl(&scu->m_pll_param); in ast2500_get_mpll_rate()
80 extern u32 ast2500_get_hpll_rate(struct ast2500_scu *scu) in ast2500_get_hpll_rate() argument
82 u32 clkin = ast2500_get_clkin(scu); in ast2500_get_hpll_rate()
83 u32 hpll_reg = readl(&scu->h_pll_param); in ast2500_get_hpll_rate()
99 extern u32 ast2500_get_dpll_rate(struct ast2500_scu *scu) in ast2500_get_dpll_rate() argument
101 u32 clkin = ast2500_get_clkin(scu); in ast2500_get_dpll_rate()
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H A Dclk_ast2400.c37 extern u32 ast2400_get_clkin(struct ast2400_scu *scu) in ast2400_get_clkin() argument
40 u32 strap = readl(&scu->hwstrap); in ast2400_get_clkin()
61 extern u32 ast2400_get_mpll_rate(struct ast2400_scu *scu) in ast2400_get_mpll_rate() argument
64 u32 clkin = ast2400_get_clkin(scu); in ast2400_get_mpll_rate()
65 u32 mpll_reg = readl(&scu->m_pll_param); in ast2400_get_mpll_rate()
91 extern u32 ast2400_get_hpll_rate(struct ast2400_scu *scu) in ast2400_get_hpll_rate() argument
94 u32 clkin = ast2400_get_clkin(scu); in ast2400_get_hpll_rate()
95 u32 hpll_reg = readl(&scu->h_pll_param); in ast2400_get_hpll_rate()
142 extern u32 ast2400_get_d2pll_rate(struct ast2400_scu *scu) in ast2400_get_d2pll_rate() argument
145 u32 clkin = ast2400_get_clkin(scu); in ast2400_get_d2pll_rate()
[all …]
/openbmc/u-boot/arch/x86/lib/
H A Dscu.c7 * microcontroller is System Controller Unit (SCU) which, in particular,
10 * This driver enables IPC channel to SCU.
17 #include <asm/scu.h>
22 /* SCU register map */
33 struct scu { struct
38 * scu_ipc_send_command() - send command to SCU
39 * @regs: register map of SCU
43 * A write to this register results in an interrupt to the SCU core processor
54 * @regs: register map of SCU
58 * block and error status of the IPC command that was just processed by SCU
[all …]
/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dfsl,scu.yaml4 $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
26 const: fsl,imx-scu
30 Clock controller node that provides the clocks controlled by the SCU
31 $ref: /schemas/clock/fsl,scu-clk.yaml
35 Control the GPIO PINs on SCU domain over the firmware APIs
40 OCOTP controller node provided by the SCU
41 $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
45 Keys provided by the SCU
46 $ref: /schemas/input/fsl,scu-key.yaml
53 channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu"
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dintel_scu_ipc.h11 * struct intel_scu_ipc_data - Data used to configure SCU IPC
12 * @mem: Base address of SCU IPC MMIO registers
13 * @irq: The IRQ number used for SCU (optional)
28 void intel_scu_ipc_unregister(struct intel_scu_ipc_dev *scu);
39 void intel_scu_ipc_dev_put(struct intel_scu_ipc_dev *scu);
42 int intel_scu_ipc_dev_ioread8(struct intel_scu_ipc_dev *scu, u16 addr,
44 int intel_scu_ipc_dev_iowrite8(struct intel_scu_ipc_dev *scu, u16 addr,
46 int intel_scu_ipc_dev_readv(struct intel_scu_ipc_dev *scu, u16 *addr,
48 int intel_scu_ipc_dev_writev(struct intel_scu_ipc_dev *scu, u16 *addr,
51 int intel_scu_ipc_dev_update(struct intel_scu_ipc_dev *scu, u16 addr,
[all …]
/openbmc/u-boot/drivers/reset/aspeed/
H A Dreset-ast2500.c18 struct ast2500_scu *scu; member
24 struct ast2500_scu *scu = priv->scu; in ast2500_reset_deassert() local
30 clrbits_le32(&scu->sysreset_ctrl2 , BIT(reset_ctl->id - 32)); in ast2500_reset_deassert()
32 clrbits_le32(&scu->sysreset_ctrl1 , BIT(reset_ctl->id)); in ast2500_reset_deassert()
40 struct ast2500_scu *scu = priv->scu; in ast2500_reset_assert() local
57 ast_scu_unlock(priv->scu); in ast2500_reset_assert()
58 setbits_le32(&priv->scu->sysreset_ctrl1, in ast2500_reset_assert()
61 clrbits_le32(&priv->scu->sysreset_ctrl1, in ast2500_reset_assert()
63 ast_scu_lock(priv->scu); in ast2500_reset_assert()
69 setbits_le32(&scu->sysreset_ctrl2 , BIT(reset_ctl->id - 32)); in ast2500_reset_assert()
[all …]
H A Dreset-ast2600.c18 struct ast2600_scu *scu; member
24 struct ast2600_scu *scu = priv->scu; in ast2600_reset_deassert() local
29 writel(BIT(reset_ctl->id - 32), &scu->sysreset_clr_ctrl2); in ast2600_reset_deassert()
31 writel(BIT(reset_ctl->id), &scu->sysreset_clr_ctrl1); in ast2600_reset_deassert()
39 struct ast2600_scu *scu = priv->scu; in ast2600_reset_assert() local
44 writel(BIT(reset_ctl->id - 32), &scu->sysreset_ctrl2); in ast2600_reset_assert()
46 writel(BIT(reset_ctl->id), &scu->sysreset_ctrl1); in ast2600_reset_assert()
65 /* find SCU base address from clock device */ in ast2600_reset_probe()
73 priv->scu = devfdt_get_addr_ptr(clk_dev); in ast2600_reset_probe()
74 if (IS_ERR(priv->scu)) { in ast2600_reset_probe()
[all …]
H A Dreset-ast2400.c15 struct ast2400_scu *scu; member
21 struct ast2400_scu *scu = priv->scu; in ast2400_reset_deassert() local
25 clrbits_le32(&scu->sysreset_ctrl1 , BIT(reset_ctl->id)); in ast2400_reset_deassert()
33 struct ast2400_scu *scu = priv->scu; in ast2400_reset_assert() local
39 setbits_le32(&scu->sysreset_ctrl1 , BIT(reset_ctl->id)); in ast2400_reset_assert()
59 /* find SCU base address from clock device */ in ast2400_reset_probe()
67 priv->scu = devfdt_get_addr_ptr(clk_dev); in ast2400_reset_probe()
68 if (IS_ERR(priv->scu)) { in ast2400_reset_probe()
69 debug("%s(): can't get SCU\n", __func__); in ast2400_reset_probe()
70 return PTR_ERR(priv->scu); in ast2400_reset_probe()
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Dfsl,scu-pd.yaml4 $id: http://devicetree.org/schemas/power/fsl,scu-pd.yaml#
7 title: i.MX SCU Client Device Node - Power Domain Based on SCU Message Protocol
12 description: i.MX SCU Client Device Node
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
14 Power domain bindings based on SCU Message Protocol
23 - fsl,imx8qm-scu-pd
24 - fsl,imx8qxp-scu-pd
25 - const: fsl,scu-pd
39 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dscu.h10 /* ARM Snoop Control Unit (SCU) registers */
12 uint scu_ctrl; /* SCU Control Register, offset 00 */
13 uint scu_cfg; /* SCU Config Register, offset 04 */
14 uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */
15 uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */
17 uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */
18 uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */
20 uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */
21 uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */
/openbmc/linux/drivers/irqchip/
H A Dirq-aspeed-scu-ic.c3 * Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller
42 struct regmap *scu; member
60 * The SCU IC has just one register to control its operation and read in aspeed_scu_ic_irq_handler()
69 regmap_read(scu_ic->scu, scu_ic->reg, &sts); in aspeed_scu_ic_irq_handler()
80 regmap_write_bits(scu_ic->scu, scu_ic->reg, mask, in aspeed_scu_ic_irq_handler()
98 regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, 0); in aspeed_scu_ic_irq_mask()
113 regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit); in aspeed_scu_ic_irq_unmask()
124 .name = "aspeed-scu-ic",
154 scu_ic->scu = syscon_node_to_regmap(node->parent); in aspeed_scu_ic_of_init_common()
155 if (IS_ERR(scu_ic->scu)) { in aspeed_scu_ic_of_init_common()
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Darm-mpcore.h12 /* SCU Control Register */
17 /* SCU Configuration Register */
19 /* SCU CPU Power Status Register */
21 /* SCU Invalidate All Registers in Secure State */
23 /* SCU Filtering Start Address Register */
25 /* SCU Filtering End Address Register */
27 /* SCU Access Control Register */
29 /* SCU Non-secure Access Control Register */
/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Dfsl,scu-ocotp.yaml4 $id: http://devicetree.org/schemas/nvmem/fsl,scu-ocotp.yaml#
7 title: i.MX SCU Client Device Node - OCOTP Based on SCU Message Protocol
12 description: i.MX SCU Client Device Node
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
21 - fsl,imx8qm-scu-ocotp
22 - fsl,imx8qxp-scu-ocotp
49 compatible = "fsl,imx8qxp-scu-ocotp";
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,scu.yaml4 $id: http://devicetree.org/schemas/arm/arm,scu.yaml#
7 title: ARM Snoop Control Unit (SCU)
28 - arm,cortex-a9-scu
29 - arm,cortex-a5-scu
30 - arm,arm11mp-scu
43 scu@a0410000 {
44 compatible = "arm,cortex-a9-scu";
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,scu-clk.yaml4 $id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
7 title: i.MX SCU Client Device Node - Clock Controller Based on SCU Message Protocol
12 description: i.MX SCU Client Device Node
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
27 - const: fsl,scu-clk
41 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
/openbmc/linux/drivers/clk/imx/
H A Dclk-scu.c18 #include "clk-scu.h"
42 * struct clk_scu - Description of one SCU clock
44 * @rsrc_id: resource ID of this SCU clock
60 * struct clk_gpr_scu - Description of one SCU GPR clock
62 * @rsrc_id: resource ID of this SCU clock
77 * @hdr: SCU protocol header
82 * This structure describes the SCU protocol of clock rate set
102 * @hdr: SCU protocol header
106 * This structure describes the SCU protocol of clock rate get
118 * @hdr: SCU protocol header
[all …]
/openbmc/linux/drivers/watchdog/
H A Dintel-mid_wdt.c3 * intel-mid_wdt: generic Intel MID SCU watchdog driver
29 /* SCU watchdog messages */
39 struct intel_scu_ipc_dev *scu; member
45 struct intel_scu_ipc_dev *scu = mid->scu; in wdt_command() local
47 return intel_scu_ipc_dev_command_with_size(scu, IPC_WATCHDOG, sub, in, in wdt_command()
62 * SCU expects the input size for watchdog IPC to be 2 which is the in wdt_start()
63 * size of the structure in dwords. SCU IPC normally takes bytes in wdt_start()
110 .identity = "Intel MID SCU watchdog",
157 mid->scu = devm_intel_scu_ipc_dev_get(dev); in mid_wdt_probe()
158 if (!mid->scu) in mid_wdt_probe()
/openbmc/linux/drivers/scsi/isci/
H A Dscu_task_context.h60 * This file contains the structures and constants for the SCU hardware task
69 * types the SCU hardware will accept. The definition for the various task
70 * types the SCU hardware will accept can be found in the DS specification.
85 * types the SCU hardware will accept. The definition for the various task
86 * types the SCU hardware will accept can be found in the DS specification.
187 * operations to construct the various SCU commands
224 * SCU_COMMAND_TYPES These constants provide the grouping of the different SCU
240 * posted to the SCU hardware.
284 * SCU_TASK_CONTEXT_PROTOCOL SCU Task context protocol types this is uesd to
285 * program the SCU Task context protocol field in word 0x00.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dfsl,scu-key.yaml4 $id: http://devicetree.org/schemas/input/fsl,scu-key.yaml#
7 title: i.MX SCU Client Device Node - SCU Key Based on SCU Message Protocol
12 description: i.MX SCU Client Device Node
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
/openbmc/u-boot/arch/arm/dts/
H A Dast2600.dtsi125 clocks = <&scu ASPEED_CLK_AHB>;
150 clocks = <&scu ASPEED_CLK_AHB>;
171 clocks = <&scu ASPEED_CLK_AHB>;
208 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
218 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
228 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
257 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>;
267 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>;
281 compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Daspeed,ast2xxx-scu-ic.txt1 Aspeed AST25XX and AST26XX SCU Interrupt Controller
5 - compatible : must be "aspeed,ast2500-scu-ic",
6 "aspeed,ast2600-scu-ic0" or
7 "aspeed,ast2600-scu-ic1"
19 compatible = "aspeed,ast2500-scu-ic";

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