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/openbmc/u-boot/arch/arm/dts/
H A Dstih407-pinctrl.dtsi9 #include "st-pincfg.h"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /* 0-5: PIO_SBC */
21 /* 10-19: PIO_FRONT0 */
34 /* 30-35: PIO_REAR */
41 /* 40-42: PIO_FLASH */
48 pin-controller-sbc {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "st,stih407-sbc-pinctrl";
[all …]
H A Drk3288-veyron.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
18 stdout-path = &uart2;
22 u-boot,dm-pre-reloc;
23 u-boot,boot0 = &spi_flash;
28 pinctrl-names = "default";
29 pinctrl-0 = <&fw_wp_ap>;
30 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
35 compatible = "pwm-backlight";
[all …]
H A Dimx7-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Copyright 2016-2019 Toradex AG
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
11 pinctrl-names = "default", "gpio";
12 pinctrl-0 = <&pinctrl_i2c1>;
13 pinctrl-1 = <&pinctrl_i2c1_gpio>;
14 sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
15 scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
25 pinctrl-names = "default", "gpio";
[all …]
H A Dimx53-kp.dts5 * SPDX-License-Identifier: GPL-2.0+ or X11
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
11 #include "imx53-pinfunc.h"
15 compatible = "kp,imx53-kp", "fsl,imx53";
18 stdout-path = &uart2;
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_eth>;
25 phy-mode = "rmii";
26 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
[all …]
H A Dkirkwood-km_common.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 stdout-path = &uart0;
9 pinctrl: pin-controller@10000 {
10 pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >;
11 pinctrl-names = "default";
13 pmx_i2c_gpio_sda: pmx-gpio-sda {
14 marvell,pins = "mpp8";
17 pmx_i2c_gpio_scl: pmx-gpio-scl {
18 marvell,pins = "mpp9";
29 compatible = "i2c-gpio";
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H A Drk3399-firefly.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
10 #include "rk3399-sdram-ddr3-1600.dtsi"
13 model = "Firefly-RK3399 Board";
14 compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
17 stdout-path = &uart2;
18 u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
22 compatible = "pwm-backlight";
[all …]
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
[all …]
H A Drk3399-gru-kevin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Kevin Rev 6+ board device tree source
5 * Copyright 2016-2017 Google, Inc
8 /dts-v1/;
9 #include "rk3399-gru-chromebook.dtsi"
10 #include <dt-bindings/input/linux-event-codes.h>
13 * Kevin-specific things
21 compatible = "google,kevin-rev15", "google,kevin-rev14",
22 "google,kevin-rev13", "google,kevin-rev12",
23 "google,kevin-rev11", "google,kevin-rev10",
[all …]
H A Dimx6ul-14x14-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
7 /dts-v1/;
13 compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
20 stdout-path = &uart1;
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <0>;
33 compatible = "regulator-fixed";
34 regulator-name = "VSD_3V3";
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H A Drk3288-veyron-minnie.dts6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
46 #include "rk3288-veyron-chromebook.dtsi"
50 compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
51 "google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
52 "google,veyron-minnie-rev0", "google,veyron-minnie",
55 backlight_regulator: backlight-regulator {
56 compatible = "regulator-fixed";
57 enable-active-high;
59 pinctrl-names = "default";
[all …]
H A Dimx6ull-colibri.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
12 compatible = "toradex,imx6ull-colibri", "fsl,imx6ull";
15 stdout-path = &uart1;
18 reg_module_3v3: regulator-module-3v3 {
19 compatible = "regulator-fixed";
20 regulator-always-on;
21 regulator-name = "+V3.3";
22 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx6ul-pcl063.dtsi1 // SPDX-License-Identifier: GPL-2.0+
10 /dts-v1/;
15 model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
16 compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
23 stdout-path = &uart1;
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_enet1>;
30 phy-mode = "rmii";
31 phy-handle = <&ethphy0>;
35 #address-cells = <1>;
[all …]
H A Dimx6ul-9x9-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
7 /dts-v1/;
13 compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul";
20 stdout-path = &uart1;
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <0>;
33 compatible = "regulator-fixed";
35 regulator-name = "can-3v3";
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H A Dat91sam9x5.dtsi2 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
13 #include <dt-bindings/dma/at91.h>
14 #include <dt-bindings/pinctrl/at91.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/at91.h>
22 interrupt-parent = <&aic>;
45 compatible = "arm,arm926ej-s";
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
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H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 u-boot,dm-pre-reloc;
15 stdout-path = "serial2:115200n8";
16 u-boot,spl-boot-order = &spi_flash;
20 u-boot,spl-payload-offset = <0x40000>;
29 * - Rails that only connect to the EC (or devices that the EC talks to)
31 * - Rails _are_ included if the rails go to the AP even if the AP
[all …]
H A Dat91sam9rl.dtsi2 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pwm/pwm.h>
19 interrupt-parent = <&aic>;
42 compatible = "arm,arm926ej-s";
53 compatible = "fixed-clock";
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H A Dsun5i-a13-utoo-p66.dts4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun5i-a13.dtsi"
45 #include "sun5i-reference-design-tablet.dtsi"
46 #include <dt-bindings/interrupt-controller/irq.h>
50 compatible = "utoo,p66", "allwinner,sun5i-a13";
52 /* The P66 uses the uart pins as gpios */
54 /delete-property/serial0;
58 /delete-property/stdout-path;
63 compatible = "i2c-gpio";
[all …]
H A Drk3399-rock960.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/pwm/pwm.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
11 vcc1v8_s0: vcc1v8-s0 {
12 compatible = "regulator-fixed";
13 regulator-name = "vcc1v8_s0";
14 regulator-min-microvolt = <1800000>;
15 regulator-max-microvolt = <1800000>;
16 regulator-always-on;
19 vcc_sys: vcc-sys {
[all …]
H A Dsun6i-a31-colombus.dts4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
46 #include "sun6i-a31.dtsi"
47 #include "sunxi-common-regulators.dtsi"
49 #include <dt-bindings/gpio/gpio.h>
53 compatible = "wits,colombus", "allwinner,sun6i-a31";
60 stdout-path = "serial0:115200n8";
65 compatible = "i2c-gpio";
66 pinctrl-names = "default";
[all …]
H A Drk3399-evb.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
10 #include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
14 compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
15 "google,rk3399evb-rev2";
18 stdout-path = &uart2;
19 u-boot,spl-boot-order = \
23 vdd_center: vdd-center {
[all …]
H A Dat91sam9261.dtsi2 * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
4 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clock/at91.h>
18 interrupt-parent = <&aic>;
38 compatible = "arm,arm926ej-s";
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
[all …]
/openbmc/u-boot/drivers/i2c/
H A Drcar_i2c.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Clock configuration based on Linux i2c-rcar.c:
8 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
9 * Copyright (C) 2011-2015 Renesas Electronics Corporation
10 * Copyright (C) 2012-14 Renesas Solutions Corp.
23 #define RCAR_I2C_ICMCR_MDBS BIT(7) /* non-fifo mode switch */
24 #define RCAR_I2C_ICMCR_FSCL BIT(6) /* override SCL pin */
26 #define RCAR_I2C_ICMCR_OBPC BIT(4) /* override pins */
50 * Defines 1st bit delay between SDA and SCL.
74 ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST, in rcar_i2c_finish()
[all …]
/openbmc/u-boot/board/liebherr/display5/
H A Ddisplay5.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mx6-ddr.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/mach-imx/spi.h>
117 gd->ram_size = imx_ddr_size(); in dram_init()
125 .scl = {
[all …]
/openbmc/u-boot/board/silica/pengwyn/
H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0+
15 /* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
19 {-1},
22 /* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
24 /* I2C pins C16(scl)/C17(sda) */
30 {-1},
33 /* MMC0 pins */
42 {-1},
45 /* MII pins */
62 {-1},
[all …]
/openbmc/u-boot/board/dhelectronics/dh_imx6/
H A Ddh_imx6.c1 // SPDX-License-Identifier: GPL-2.0+
3 * DHCOM DH-iMX6 PDK board support
12 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/sata.h>
32 #include <usb/ehci-ci.h>
45 .scl = {
[all …]

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