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/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub
30 clock-names:
38 "#address-cells":
41 "#size-cells":
[all …]
/openbmc/qemu/hw/ppc/
H A Dppc440_uc.c5 * Copyright (c) 2016-2019 BALATON Zoltan
17 #include "hw/pci-host/ppc4xx.h"
18 #include "hw/qdev-properties.h"
40 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
91 ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; in dcr_read_l2sram()
105 ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; in dcr_read_l2sram()
129 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/ in dcr_write_l2sram()
143 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/ in dcr_write_l2sram()
154 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/ in dcr_write_l2sram()
163 memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache)); in l2sram_reset()
[all …]
/openbmc/linux/drivers/soc/versatile/
H A Dsoc-integrator.c1 // SPDX-License-Identifier: GPL-2.0-only
21 { .compatible = "arm,core-module-integrator", },
29 return "ASB little-endian"; in integrator_arch_str()
31 return "AHB little-endian"; in integrator_arch_str()
33 return "AHB-Lite system bus, bi-endian"; in integrator_arch_str()
35 return "AHB"; in integrator_arch_str()
37 return "AHB system bus, ASB processor bus"; in integrator_arch_str()
70 return sprintf(buf, "%s\n", integrator_arch_str(integrator_coreid)); in arch_show()
78 return sprintf(buf, "%s\n", integrator_fpga_str(integrator_coreid)); in fpga_show()
113 return -ENODEV; in integrator_soc_init()
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx35.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
33 unsigned char arm, ahb, sel; member
37 { .arm = 1, .ahb = 4, .sel = 0},
38 { .arm = 1, .ahb = 3, .sel = 1},
39 { .arm = 2, .ahb = 2, .sel = 0},
40 { .arm = 0, .ahb = 0, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 4, .ahb = 1, .sel = 0},
[all …]
H A Dclk-imx25.c1 // SPDX-License-Identifier: GPL-2.0-or-later
47 static const char *per_sel_clks[] = { "ahb", "upll", };
48 static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
54 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
89 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
141 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
143 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
144 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
145 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); in __mx25_clocks_init()
[all …]
H A Dclk-imx31.c1 // SPDX-License-Identifier: GPL-2.0-or-later
39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
63 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in _mx31_clocks_init()
64 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); in _mx31_clocks_init()
65 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); in _mx31_clocks_init()
82 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); in _mx31_clocks_init()
100 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); in _mx31_clocks_init()
111 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); in _mx31_clocks_init()
112 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); in _mx31_clocks_init()
130 for_each_compatible_node(osc_np, NULL, "fixed-clock") { in mx31_clocks_init_dt()
[all …]
/openbmc/linux/drivers/clk/microchip/
H A Dclk-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/microchip,mpfs-clock.h>
99 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
100 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
101 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; in mpfs_clk_msspll_recalc_rate()
117 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_round_rate()
118 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_round_rate()
130 msspll_hw->flags); in mpfs_clk_msspll_round_rate()
[all …]
/openbmc/linux/drivers/pci/controller/
H A Dpci-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver
9 * Copyright (C) 2003 Greg Ungerer <gerg@linux-m68k.org>
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
15 * - Test IO-space access
16 * - DMA support
113 * operates in big-endian or little-endian mode. That means that
114 * readl() and writel() that always use little-endian access
116 * when used in big-endian mode. The accesses to the individual
117 * PCI devices on the other hand, are always little-endian and
[all …]
H A Dpci-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-rcar-gen2: internal PCI bus support
26 /* AHB-PCI Bridge PCI communication registers */
108 struct rcar_pci *priv = bus->sysdata; in rcar_pci_cfg_base()
114 /* Only one EHCI/OHCI device built-in */ in rcar_pci_cfg_base()
126 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); in rcar_pci_cfg_base()
127 return priv->reg + (slot >> 1) * 0x100 + where; in rcar_pci_cfg_base()
136 struct device *dev = priv->dev; in rcar_pci_err_irq()
137 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); in rcar_pci_err_irq()
142 /* clear the error(s) */ in rcar_pci_err_irq()
[all …]
/openbmc/phosphor-mrw-tools/
H A Dgen_callouts.pl18 "m=s" => \$mrwFile,
19 "o=s" => \$outFile,
31 my $targets = Targets->new;
32 $targets->loadXML($mrwFile);
40 my $i2cPath = "/sys/devices/platform/ahb/ahb:apb/ahb:apb:bus\@1e78a000/1e78a100.i2c-bus/i2c-<port>/…
41 my $fsiMasterPath = "/sys/devices/platform/gpio-fsi/fsi0/slave\@00:00/raw";
42 my $fsiSlavePath = "/sys/devices/platform/gpio-fsi/fsi0/slave\@00:00/00:00:00:0a/fsi1/slave\@<link>…
56 my $connections = $targets->findConnections($bmc, "I2C");
57 # hash of arrays - {I2C master port : list of connected slave Targets}
60 for my $i2c (@{$connections->{CONN}})
[all …]
/openbmc/linux/drivers/media/platform/qcom/camss/
H A Dcamss.c1 // SPDX-License-Identifier: GPL-2.0
5 * Qualcomm MSM Camera Subsystem - Core
8 * Copyright (C) 2015-2018 Linaro Ltd.
12 #include <linux/media-bus-format.h>
23 #include <media/media-device.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-mc.h>
27 #include <media/v4l2-fwnode.h>
38 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
[all …]
/openbmc/qemu/include/hw/misc/
H A Daspeed_scu.h9 * the COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
67 uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg);
68 uint32_t (*get_apb)(AspeedSCUState *s);
77 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_matrix.h1 /* SPDX-License-Identifier: GPL-2.0+ */
58 u32 reserve1[16 - AT91_MATRIX_MASTERS];
60 u32 reserve2[16 - AT91_MATRIX_SLAVES];
62 u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
66 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
100 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
102 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
151 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
153 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
222 /* USB Pad Pull-Up Control Register */
/openbmc/u-boot/include/faraday/
H A Dftpci100.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 /* AHB Control Registers */
15 unsigned int iosize; /* 0x00 - I/O Space Size Signal */
16 unsigned int prot; /* 0x04 - AHB Protection */
17 unsigned int rsved[8]; /* 0x08-0x24 - Reserved */
18 unsigned int conf; /* 0x28 - PCI Configuration */
19 unsigned int data; /* 0x2c - PCI Configuration DATA */
23 * FTPCI100_IOSIZE_REG's constant definitions
25 #define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */
36 * PCI_INT_MASK's bit definitions
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
19 that is, MSI clock and AHB clock, need to be enabled so that peripherals
30 So, the controller's registers cannot be accessed by SCFW user. Hence,
32 user's point of view.
35 - $ref: simple-pm-bus.yaml#
[all …]
/openbmc/linux/drivers/usb/host/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
31 * This Software, including technical data, may be subject to U.S. export
32 * control laws, including the U.S. Export Administration Act and its associated
102 * Core AHB Configuration Register (GAHBCFG)
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
106 * configuration parameters. The AHB is the processor interface to the O2P USB
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
[all …]
/openbmc/phosphor-pid-control/
H A Dconfigure.md1 # How to Configure Phosphor-pid-control
5 They can come either from a dedicated config file or via D-Bus from e.g.
6 `entity-manager`.
8 ## D-Bus Configuration
10 If config file does not exist the configuration is obtained from a set of D-Bus
11 interfaces. When using `entity-manager` to provide them refer to `Pid`,
13 [schemas](https://github.com/openbmc/entity-manager/tree/master/schemas). The
19 ### --strict-failsafe-pwm
26 ### --offline-failsafe-pwm
29 controller is offline when it's rebuilding the configuration or when it's about
[all …]
/openbmc/phosphor-pid-control/test/
H A Dsensors_json_unittest.cpp28 // If the json has one sensor, it's in the map. in TEST()
36 … "writePath": "/sys/devices/platform/ahb/ahb:apb/1e786000.pwm-tacho-controller/hwmon/**/pwm1", in TEST()
49 "/sys/devices/platform/ahb/ahb:apb/1e786000.pwm-tacho-controller/" in TEST()
/openbmc/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx-lcdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
11 - Pengutronix Kernel Team <kernel@pengutronix.de>
16 - enum:
17 - fsl,imx1-fb
18 - fsl,imx21-fb
19 - items:
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Ddebugfs-driver-dcc6 hardware if it's ready to receive user configurations.
27 What: /sys/kernel/debug/dcc/.../[list-number]/config
35 write, read-write, and loop type. The lists need to
45 echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config
58 The bus type, which can be either 'apb' or 'ahb'.
59 The default is 'ahb' if leaved out.
65 echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config
76 The bus type, which can be either 'apb' or 'ahb'.
78 iii) Read-write instruction
82 echo RW <addr> <n> <mask> > /sys/kernel/debug/dcc/../[list-number]/config
[all …]
/openbmc/linux/arch/mips/ath25/
H A Dar2315_regs.h11 * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
81 #define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
82 #define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
92 /* AHB master arbitration control */
97 #define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
106 #define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
108 #define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
128 /* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
163 #define AR2315_ISR_AHB 0x00000008 /* AHB error */
172 #define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
[all …]
H A Dar5312.c9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
65 pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", in ar5312_ahb_err_handler()
68 machine_restart("AHB error"); /* Catastrophic failure */ in ar5312_ahb_err_handler()
96 ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq)); in ar5312_misc_irq_unmask()
102 ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0); in ar5312_misc_irq_mask()
107 .name = "ar5312-misc",
152 if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error", in ar5312_arch_init_irq()
154 pr_err("Failed to register ar5312-ahb-error interrupt\n"); in ar5312_arch_init_irq()
168 .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
173 .name = "physmap-flash",
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15 - "snps,dwc-qos-ethernet-4.10"
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
21 same order. See ../clock/clock-bindings.txt.
22 - clock-names: May contain any/all of the following depending on the IP
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dahb.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
14 #include "ahb.h"
17 { .compatible = "qcom,ipq4019-wifi",
30 return &ath10k_pci_priv(ar)->ahb[0]; in ath10k_ahb_priv()
37 iowrite32(value, ar_ahb->mem + offset); in ath10k_ahb_write32()
44 return ioread32(ar_ahb->mem + offset); in ath10k_ahb_read32()
51 return ioread32(ar_ahb->gcc_mem + offset); in ath10k_ahb_gcc_read32()
58 iowrite32(value, ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_write32()
65 return ioread32(ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_read32()
[all …]

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