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/openbmc/linux/drivers/staging/axis-fifo/
H A Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@foss.st.com>
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
34 st,hw-flow-ctrl:
38 rx-tx-swap: true
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H A Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
19 where N is the port number (non-negative decimal integer) as printed on the
28 cts-gpios:
34 dcd-gpios:
40 dsr-gpios:
46 dtr-gpios:
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/openbmc/linux/include/linux/soc/ti/
H A Dknav_dma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 #define MASK(x) (BIT(x) - 1)
54 /* Rx channel error handling mode during buffer starvation */
60 /* Rx flow size threshold configuration */
87 * struct knav_dma_rx_cfg: Rx flow configuration
95 * @thresh: Rx flow size threshold
97 * @sz_thresh0: RX packet size threshold 0
98 * @sz_thresh1: RX packet size threshold 1
99 * @sz_thresh2: RX packet size threshold 2
120 * @rx: Rx flow configuration
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/openbmc/linux/drivers/media/rc/
H A Dsunxi-cir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
8 * Based on sun5i-ir.c:
9 * Copyright (C) 2007-2012 Daniel Wang
19 #include <media/rc-core.h>
21 #define SUNXI_IR_DEV "sunxi-ir"
28 /* RX block enable */
33 /* Rx Config */
38 /* Rx Data */
41 /* Rx Interrupt Enable */
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* N-PHY registers. */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
21 #define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */
22 #define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */
57 #define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
70 #define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */
[all …]
H A Dphy_a.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */
11 #define B43_PHY_BBANDCFG_RXANT 0x180 /* RX Antenna selection */
14 #define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 (phy.rev 1 only) */
22 #define B43_PHY_ANTDWELL_AUTODIV1 0x0100 /* Automatic RX diversity start antenna */
40 #define B43_PHY_NRSSITHRES B43_PHY_OFDM(0x8A) /* NRSSI threshold */
42 #define B43_PHY_ANTWRSETT_ARXDIV 0x2000 /* Automatic RX diversity enabled */
43 #define B43_PHY_CLIPPWRDOWNT B43_PHY_OFDM(0x93) /* Clip powerdown threshold */
58 #define B43_PHY_CRSTHRES1 B43_PHY_OFDM(0xC0) /* CRS Threshold 1 (phy.rev >= 2 only) */
59 #define B43_PHY_CRSTHRES2 B43_PHY_OFDM(0xC1) /* CRS Threshold 2 (phy.rev >= 2 only) */
/openbmc/linux/sound/soc/ti/
H A Domap-mcbsp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
24 #include "omap-mcbsp-priv.h"
25 #include "omap-mcbsp.h"
26 #include "sdma-pcm.h"
41 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); in omap_mcbsp_dump_reg()
42 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2)); in omap_mcbsp_dump_reg()
43 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1)); in omap_mcbsp_dump_reg()
44 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2)); in omap_mcbsp_dump_reg()
45 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1)); in omap_mcbsp_dump_reg()
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dpower.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
13 * enum iwl_ltr_config_flags - masks for LTR config command flags
39 * struct iwl_ltr_config_cmd_v1 - configures the LTR
53 * struct iwl_ltr_config_cmd - configures the LTR
58 * TX, RX, Short Idle, Long Idle. Used only if %LTR_CFG_FLAG_UPDATE_VALUES
71 /* Radio LP RX Energy Threshold measured in dBm */
77 * enum iwl_power_flags - masks for power table command flags
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/openbmc/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2500pci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
36 * Default offset is required for RSSI <-> dBm conversion.
128 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
129 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
130 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
132 * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
133 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
134 * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
135 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
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/openbmc/linux/drivers/net/ethernet/intel/igb/
H A De1000_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
7 #define E1000_CTRL 0x00000 /* Device Control - RW */
8 #define E1000_STATUS 0x00008 /* Device Status - RO */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,wcd938x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire slave devices.
17 - $ref: dai-common.yaml#
22 - qcom,wcd9380-codec
23 - qcom,wcd9385-codec
25 reset-gpios:
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H A Ddavinci-mcasp-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/davinci-mcasp-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jayesh Choudhary <j-choudhary@ti.com>
15 - ti,dm646x-mcasp-audio
16 - ti,da830-mcasp-audio
17 - ti,am33xx-mcasp-audio
18 - ti,dra7-mcasp-audio
19 - ti,omap4-mcasp-audio
[all …]
/openbmc/linux/sound/soc/tegra/
H A Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
74 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
84 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
85 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
95 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
104 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
107 regcache_sync(asrc->regmap); in tegra186_asrc_runtime_resume()
110 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
42 "#address-cells":
45 "#size-cells":
48 vdda1v1-supply:
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/openbmc/linux/include/linux/platform_data/
H A Dxilinx-ll-temac.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 bool rxcsum; /* Enable/disable RX checksum */
20 /* Pre-initialized mutex to use for synchronizing indirect
27 u8 tx_irq_timeout; /* TX Interrupt Delay Time-out */
28 u8 tx_irq_count; /* TX Interrupt Coalescing Threshold Count */
29 u8 rx_irq_timeout; /* RX Interrupt Delay Time-out */
30 u8 rx_irq_count; /* RX Interrupt Coalescing Threshold Count */
/openbmc/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 1999 - 2010 Intel Corporation.
26 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
35 * pch_udc_regs - Structure holding values of MAC registers
119 #define PCH_GBE_RX_RST 0x00004000 /* RX MAC, RX FIFO, RX DMA reset */
123 #define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 /* RX TCP/IP ACC Disabled */
125 #define PCH_GBE_RX_TCPIPACC_EN 0x00000001 /* RX TCP/IP ACC Enable */
127 /* MAC RX Enable */
130 /* RX Flow Control */
136 /* RX Mode */
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/openbmc/linux/drivers/spi/
H A Dspi-pxa2xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 #include "spi-pxa2xx.h"
36 MODULE_ALIAS("platform:pxa2xx-spi");
78 /* LPSS offset from drv_data->ioaddr */
80 /* Register offsets from drv_data->lpss_base or -1 */
104 .reg_capabilities = -1,
114 .reg_capabilities = -1,
124 .reg_capabilities = -1,
134 .reg_general = -1,
137 .reg_capabilities = -1,
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Ddefines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
64 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
125 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */
131 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
132 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
133 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
[all …]
/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
59 /* get rx dma good octet counter */
62 /* get rx dma good packet counter */
71 /* get msm rx errors counter register */
74 /* get msm rx unicast frames counter register */
77 /* get msm rx multicast frames counter register */
80 /* get msm rx broadcast frames counter register */
83 /* get msm rx broadcast octets counter register 1 */
[all …]
/openbmc/qemu/hw/net/
H A De1000x_regs.h4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
115 * RW - register is both readable and writable
116 * RO - register is read only
117 * WO - register is write only
118 * R/clr - register is read only and is cleared when read
119 * A - register array
121 #define E1000_CTRL 0x00000 /* Device Control - RW */
122 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
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/openbmc/linux/drivers/net/ethernet/altera/
H A Daltera_tse.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
33 #define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in
36 /* Rx FIFO default settings */
120 u32 auto_negotiation_advertisement; /* Auto-negotiation
172 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
176 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
180 /* 14-bit maximum frame length. The MAC receive logic */
186 /* 12-bit receive FIFO section-empty threshold */
[all …]
/openbmc/u-boot/drivers/net/
H A Dftmac110.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Dante Su <dantesu@faraday-tech.com>
18 uint32_t rxpd; /* 0x1c: Rx Poll Demand Register */
20 uint32_t rxba; /* 0x24: Rx Ring Base Address Register */
41 #define ISR_RXLOST (1 << 7) /* rx lost */
42 #define ISR_RXFIFO (1 << 6) /* rx to fifo */
47 #define ISR_NORXBUF (1 << 1) /* out of rx buffer */
48 #define ISR_RXOK (1 << 0) /* rx to buffer */
54 #define MACCR_RXBCST (1 << 17) /* rx broadcast packet */
55 #define MACCR_RXMCST (1 << 16) /* rx multicast packet */
[all …]
/openbmc/linux/drivers/net/wireless/ti/wlcore/
H A Dconf.h1 /* SPDX-License-Identifier: GPL-2.0-only */
117 * Range: 0 - 0xFFFFFFFF
122 * Packet detection threshold in the PHY.
130 * after a PS-poll has been transmitted.
132 * Range: 0 - 200000
139 * Range: 0 - 200000
147 * Range: 0 - 4096
152 * The RX Clear Channel Assessment threshold in the PHY
153 * (the energy threshold).
161 * Occupied Rx mem-blocks number which requires interrupting the host
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