Home
last modified time | relevance | path

Searched +full:rockchip +full:- +full:emmc +full:- +full:phy (Results 1 – 25 of 94) sorted by relevance

1234

/openbmc/linux/drivers/phy/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
19 associated to the Rockchip ISP module present in RK3399 SoCs.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
[all …]
H A Dphy-rockchip-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip emmc PHY driver
5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
6 * Copyright (C) 2016 ROCKCHIP, Inc.
15 #include <linux/phy/phy.h>
20 * The higher 16-bit of this register is used for write protection
93 static int rockchip_emmc_phy_power(struct phy *phy, bool on_off) in rockchip_emmc_phy_power() argument
95 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); in rockchip_emmc_phy_power()
106 regmap_write(rk_phy->reg_base, in rockchip_emmc_phy_power()
107 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
3 obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o
4 obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
5 obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o
6 obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
7 obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
8 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
9 obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
10 obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drockchip-emmc-phy.txt1 Rockchip EMMC PHY
2 -----------------------
5 - compatible: rockchip,rk3399-emmc-phy
6 - #phy-cells: must be 0
7 - reg: PHY register address offset and length in "general
11 - clock-names: Should contain "emmcclk". Although this is listed as optional
14 See ../clock/clock-bindings.txt for details.
15 - clocks: Should have a phandle to the card clock exported by the SDHCI driver.
16 - drive-impedance-ohm: Specifies the drive impedance in Ohm.
19 - rockchip,enable-strobe-pulldown: Enable internal pull-down for the strobe
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3228-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
8 model = "Rockchip RK3228 Evaluation board";
9 compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
12 mmc0 = &emmc;
20 vcc_phy: vcc-phy-regulator {
21 compatible = "regulator-fixed";
22 enable-active-high;
23 regulator-name = "vcc_phy";
24 regulator-min-microvolt = <1800000>;
[all …]
H A Drk3288-phycore-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device tree file for Phytec phyCORE-RK3288 SoM
8 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
29 ext_gmac: external-gmac-clock {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <125000000>;
33 clock-output-names = "ext_gmac";
36 leds: user-leds {
[all …]
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
13 compatible = "rockchip,rk3128";
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
[all …]
H A Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
14 compatible = "rockchip,rk3066a";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
[all …]
H A Drk3288-veyron.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
14 mmc0 = &emmc;
18 stdout-path = "serial2:115200n8";
31 power_button: power-button {
32 compatible = "gpio-keys";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pwr_key_l>;
36 key-power {
[all …]
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
14 compatible = "rockchip,rk3188";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
[all …]
H A Drk3229-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/input/input.h>
9 model = "Rockchip RK3229 Evaluation board";
10 compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
13 mmc0 = &emmc;
21 dc_12v: dc-12v-regulator {
22 compatible = "regulator-fixed";
23 regulator-name = "dc_12v";
24 regulator-always-on;
[all …]
H A Drk3288-rock2-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/pwm/pwm.h>
12 emmc_pwrseq: emmc-pwrseq {
13 compatible = "mmc-pwrseq-emmc";
14 pinctrl-0 = <&emmc_reset>;
15 pinctrl-names = "default";
16 reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
19 ext_gmac: external-gmac-clock {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3188.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
13 compatible = "rockchip,rk3188";
16 #address-cells = <1>;
17 #size-cells = <0>;
18 enable-method = "rockchip,rk3066-smp";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
[all …]
H A Drv1108.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/rv1108-cru.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 compatible = "rockchip,rv1108";
[all …]
H A Drk3288-phycore-som.dtsi2 * Device tree file for Phytec phyCORE-RK3288 SoM
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/net/ti-dp83867.h>
50 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
67 ext_gmac: external-gmac-clock {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <125000000>;
71 clock-output-names = "ext_gmac";
75 compatible = "rockchip,rk3288-io-voltage-domain";
[all …]
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3128-cru.h>
14 compatible = "rockchip,rk3128";
15 rockchip,sram = <&sram>;
16 interrupt-parent = <&gic>;
[all …]
H A Drk3288.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power-domain/rk3288.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/video/rk3288.h>
14 compatible = "rockchip,rk3288";
[all …]
H A Drk3288-rock2-som.dtsi2 * This file is dual-licensed: you can use it either under the terms
41 #include <dt-bindings/pwm/pwm.h>
50 emmc_pwrseq: emmc-pwrseq {
51 compatible = "mmc-pwrseq-emmc";
52 pinctrl-0 = <&emmc_reset>;
53 pinctrl-names = "default";
54 reset-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
57 ext_gmac: external-gmac-clock {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3368-evb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2015 Caesar Wang <wxt@rock-chips.com>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pwm/pwm.h>
12 mmc0 = &emmc;
16 stdout-path = "serial2:115200n8";
25 compatible = "pwm-backlight";
26 brightness-levels = <
59 default-brightness-level = <128>;
60 enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
[all …]
H A Drk3368-r88.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
11 model = "Rockchip R88";
12 compatible = "rockchip,r88", "rockchip,rk3368";
16 mmc1 = &emmc;
20 stdout-path = "serial2:115200n8";
28 emmc_pwrseq: emmc-pwrseq {
29 compatible = "mmc-pwrseq-emmc";
30 pinctrl-0 = <&emmc_reset>;
[all …]
H A Drk3368-orion-r68-meta.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
11 model = "Rockchip Orion R68";
12 compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
16 mmc1 = &emmc;
20 stdout-path = "serial2:115200n8";
28 emmc_pwrseq: emmc-pwrseq {
29 compatible = "mmc-pwrseq-emmc";
30 pinctrl-0 = <&emmc_reset>;
[all …]
H A Dpx30-ringneck.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
12 mmc0 = &emmc;
18 emmc_pwrseq: emmc-pwrseq {
19 compatible = "mmc-pwrseq-emmc";
20 pinctrl-0 = <&emmc_reset>;
21 pinctrl-names = "default";
22 reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
26 compatible = "gpio-leds";
[all …]
H A Drk3308-rock-pi-s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
14 compatible = "radxa,rockpis", "rockchip,rk3308";
18 mmc0 = &emmc;
24 stdout-path = "serial0:1500000n8";
28 compatible = "gpio-leds";
29 pinctrl-names = "default";
30 pinctrl-0 = <&green_led>, <&heartbeat_led>;
32 green-led {
[all …]
H A Drk3328.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
[all …]

1234