1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*724ba675SRob Herring 3*724ba675SRob Herring/dts-v1/; 4*724ba675SRob Herring 5*724ba675SRob Herring#include "rk322x.dtsi" 6*724ba675SRob Herring 7*724ba675SRob Herring/ { 8*724ba675SRob Herring model = "Rockchip RK3228 Evaluation board"; 9*724ba675SRob Herring compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; 10*724ba675SRob Herring 11*724ba675SRob Herring aliases { 12*724ba675SRob Herring mmc0 = &emmc; 13*724ba675SRob Herring }; 14*724ba675SRob Herring 15*724ba675SRob Herring memory@60000000 { 16*724ba675SRob Herring device_type = "memory"; 17*724ba675SRob Herring reg = <0x60000000 0x40000000>; 18*724ba675SRob Herring }; 19*724ba675SRob Herring 20*724ba675SRob Herring vcc_phy: vcc-phy-regulator { 21*724ba675SRob Herring compatible = "regulator-fixed"; 22*724ba675SRob Herring enable-active-high; 23*724ba675SRob Herring regulator-name = "vcc_phy"; 24*724ba675SRob Herring regulator-min-microvolt = <1800000>; 25*724ba675SRob Herring regulator-max-microvolt = <1800000>; 26*724ba675SRob Herring regulator-always-on; 27*724ba675SRob Herring regulator-boot-on; 28*724ba675SRob Herring }; 29*724ba675SRob Herring}; 30*724ba675SRob Herring 31*724ba675SRob Herring&emmc { 32*724ba675SRob Herring cap-mmc-highspeed; 33*724ba675SRob Herring mmc-ddr-1_8v; 34*724ba675SRob Herring disable-wp; 35*724ba675SRob Herring non-removable; 36*724ba675SRob Herring status = "okay"; 37*724ba675SRob Herring}; 38*724ba675SRob Herring 39*724ba675SRob Herring&gmac { 40*724ba675SRob Herring assigned-clocks = <&cru SCLK_MAC_SRC>; 41*724ba675SRob Herring assigned-clock-rates = <50000000>; 42*724ba675SRob Herring clock_in_out = "output"; 43*724ba675SRob Herring phy-supply = <&vcc_phy>; 44*724ba675SRob Herring phy-mode = "rmii"; 45*724ba675SRob Herring phy-handle = <&phy>; 46*724ba675SRob Herring status = "okay"; 47*724ba675SRob Herring 48*724ba675SRob Herring mdio { 49*724ba675SRob Herring compatible = "snps,dwmac-mdio"; 50*724ba675SRob Herring #address-cells = <1>; 51*724ba675SRob Herring #size-cells = <0>; 52*724ba675SRob Herring 53*724ba675SRob Herring phy: ethernet-phy@0 { 54*724ba675SRob Herring compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 55*724ba675SRob Herring reg = <0>; 56*724ba675SRob Herring clocks = <&cru SCLK_MAC_PHY>; 57*724ba675SRob Herring resets = <&cru SRST_MACPHY>; 58*724ba675SRob Herring phy-is-integrated; 59*724ba675SRob Herring }; 60*724ba675SRob Herring }; 61*724ba675SRob Herring}; 62*724ba675SRob Herring 63*724ba675SRob Herring&tsadc { 64*724ba675SRob Herring status = "okay"; 65*724ba675SRob Herring 66*724ba675SRob Herring rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 67*724ba675SRob Herring rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 68*724ba675SRob Herring}; 69*724ba675SRob Herring 70*724ba675SRob Herring&uart2 { 71*724ba675SRob Herring status = "okay"; 72*724ba675SRob Herring}; 73