/openbmc/linux/Documentation/devicetree/bindings/power/ |
H A D | rockchip-io-domain.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/power/rockchip-io-domain.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 42 to report their voltage. The IO Voltage Domain for any non-specified 48 - rockchip,px30-io-voltage-domain 49 - rockchip,px30-pmu-io-voltage-domain 50 - rockchip,rk3188-io-voltage-domain 51 - rockchip,rk3228-io-voltage-domain [all …]
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H A D | rockchip,power-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Elaine Zhang <zhangqing@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 18 Power domains contained within power-controller node are 20 Documentation/devicetree/bindings/power/power-domain.yaml. 23 "power-domains" property that is a phandle for the 28 const: power-controller [all …]
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/openbmc/linux/Documentation/devicetree/bindings/arm/rockchip/ |
H A D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip Power Management Unit (PMU) 10 - Elaine Zhang <zhangqing@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 14 The PMU is used to turn on and off different power domains of the SoCs. 22 - rockchip,px30-pmu 23 - rockchip,rk3066-pmu [all …]
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/openbmc/linux/Documentation/devicetree/bindings/devfreq/event/ |
H A D | rockchip-dfi.txt | 2 * Rockchip rk3399 DFI device 5 - compatible: Must be "rockchip,rk3399-dfi". 6 - reg: physical base address of each DFI and length of memory mapped region 7 - rockchip,pmu: phandle to the syscon managing the "pmu general register files" 8 - clocks: phandles for clock specified in "clock-names" property 9 - clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon"; 13 compatible = "rockchip,rk3399-dfi"; 15 rockchip,pmu = <&pmugrf>; 17 clock-names = "pclk_ddr_mon";
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/openbmc/u-boot/board/theobroma-systems/puma_rk3399/ |
H A D | fit_spl_atf.its | 1 /* SPDX-License-Identifier: GPL-2.0+ OR X11 */ 8 /dts-v1/; 11 description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB"; 12 #address-cells = <1>; 16 description = "U-Boot (64-bit)"; 17 data = /incbin/("../../../u-boot-nodtb.bin"); 19 os = "U-Boot"; 26 data = /incbin/("../../../bl31-rk3399.bin"); 29 os = "arm-trusted-firmware"; 34 pmu { [all …]
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device 10 - Brian Norris <briannorris@chromium.org> 15 - rockchip,rk3399-dmc 17 devfreq-events: 21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt. 26 clock-names: [all …]
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/openbmc/u-boot/drivers/pinctrl/rockchip/ |
H A D | pinctrl-rk3399.c | 1 // SPDX-License-Identifier: GPL-2.0+ 12 #include "pinctrl-rockchip.h" 60 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3399_calc_pull_reg_and_bit() 62 /* The bank0:16 and bank1:32 pins are located in PMU */ in rk3399_calc_pull_reg_and_bit() 63 if (bank->bank_num == 0 || bank->bank_num == 1) { in rk3399_calc_pull_reg_and_bit() 64 *regmap = priv->regmap_pmu; in rk3399_calc_pull_reg_and_bit() 67 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit() 73 *regmap = priv->regmap_base; in rk3399_calc_pull_reg_and_bit() 77 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit() 78 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit() [all …]
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H A D | pinctrl-rockchip-core.c | 1 // SPDX-License-Identifier: GPL-2.0+ 13 #include "pinctrl-rockchip.h" 22 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config() 24 if (bank >= ctrl->nr_banks) { in rockchip_verify_config() 25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config() 26 return -EINVAL; in rockchip_verify_config() 32 return -EINVAL; in rockchip_verify_config() 41 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_get_recalced_mux() 42 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_recalced_mux() 46 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux() [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | rk3399.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd. 6 #include <dt-bindings/clock/rk3399-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rk3399-power.h> 12 #include <dt-bindings/thermal/thermal.h> 16 compatible = "rockchip,rk3399"; [all …]
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H A D | rv1108.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/interrupt-controller/irq.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/rv1108-cru.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 12 #address-cells = <1>; 13 #size-cells = <1>; 17 interrupt-parent = <&gic>; 27 #address-cells = <1>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3399.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rk3399-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rk3399-power.h> 12 #include <dt-bindings/thermal/thermal.h> 15 compatible = "rockchip,rk3399"; 17 interrupt-parent = <&gic>; [all …]
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H A D | rk356x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rk3568-cru.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rk3568-power.h> 12 #include <dt-bindings/soc/rockchip,boot-mode.h> 13 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; [all …]
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H A D | rk3588s.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rockchip,rk3588-cru.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/power/rk3588-power.h> 10 #include <dt-bindings/reset/rockchip,rk3588-cru.h> 11 #include <dt-bindings/phy/phy.h> 12 #include <dt-bindings/ata/ahci.h> 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; [all …]
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H A D | px30.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/px30-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/px30-power.h> 12 #include <dt-bindings/soc/rockchip,boot-mode.h> 13 #include <dt-bindings/thermal/thermal.h> 18 interrupt-parent = <&gic>; [all …]
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H A D | rk3328.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rk3328-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rk3328-power.h> 12 #include <dt-bindings/soc/rockchip,boot-mode.h> 13 #include <dt-bindings/thermal/thermal.h> 18 interrupt-parent = <&gic>; [all …]
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/openbmc/u-boot/board/vamrs/rock960_rk3399/ |
H A D | README | 6 3. Compile the U-Boot 9 5.1. Package the image for U-Boot SPL(option 1) 13 7.1. Flash the image with U-Boot SPL(option 1) 22 Ficus (Enterprise Edition) 96Boards featuring Rockchip RK3399 SoC. 25 * CPU: ARMv8 64bit Big-Little architecture, 26 * Big: dual-core Cortex-A72 27 * Little: quad-core Cortex-A53 30 * PMU: RK808 47 Here is the step-by-step to boot to U-Boot on Rock960 boards. 53 > git clone https://github.com/rockchip-linux/rkdeveloptool.git [all …]
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/openbmc/linux/drivers/soc/rockchip/ |
H A D | io-domain.c | 1 // SPDX-License-Identifier: GPL-2.0-only 26 * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the 28 * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider 84 struct rockchip_iodomain *iod = supply->iod; in rk3568_iodomain_write() 89 switch (supply->idx) { in rk3568_iodomain_write() 93 b = supply->idx; in rk3568_iodomain_write() 95 b = supply->idx + 4; in rk3568_iodomain_write() 98 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val0); in rk3568_iodomain_write() 99 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val1); in rk3568_iodomain_write() 109 b = supply->idx - 1; in rk3568_iodomain_write() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | rockchip,pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 18 Please refer to pinctrl-bindings.txt in this directory for details of the 26 various pad settings such as pull-up, etc. 29 defined as gpio sub-nodes of the pinmux controller. 34 - rockchip,px30-pinctrl 35 - rockchip,rk2928-pinctrl 36 - rockchip,rk3036-pinctrl [all …]
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/openbmc/linux/drivers/devfreq/ |
H A D | rk3399_dmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Author: Lin Huang <hl@rock-chips.com> 7 #include <linux/arm-smccc.h> 12 #include <linux/devfreq-event.h> 74 unsigned long old_clk_rate = dmcfreq->rate; in rk3399_dmcfreq_target() 92 if (dmcfreq->rate == target_rate) in rk3399_dmcfreq_target() 95 mutex_lock(&dmcfreq->lock); in rk3399_dmcfreq_target() 98 * Ensure power-domain transitions don't interfere with ARM Trusted in rk3399_dmcfreq_target() 99 * Firmware power-domain idling. in rk3399_dmcfreq_target() 103 dev_err(dev, "Failed to block PMU: %d\n", err); in rk3399_dmcfreq_target() [all …]
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/openbmc/linux/arch/arm/boot/dts/rockchip/ |
H A D | rv1126.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rockchip,rv1126-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rockchip,rv1126-power.h> 12 #include <dt-bindings/soc/rockchip,boot-mode.h> 15 #address-cells = <1>; 16 #size-cells = <1>; [all …]
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/openbmc/linux/drivers/pmdomain/rockchip/ |
H A D | pm-domains.c | 1 // SPDX-License-Identifier: GPL-2.0-only 21 #include <dt-bindings/power/px30-power.h> 22 #include <dt-bindings/power/rockchip,rv1126-power.h> 23 #include <dt-bindings/power/rk3036-power.h> 24 #include <dt-bindings/power/rk3066-power.h> 25 #include <dt-bindings/power/rk3128-power.h> 26 #include <dt-bindings/power/rk3188-power.h> 27 #include <dt-bindings/power/rk3228-power.h> 28 #include <dt-bindings/power/rk3288-power.h> 29 #include <dt-bindings/power/rk3328-power.h> [all …]
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/openbmc/linux/drivers/devfreq/event/ |
H A D | rockchip-dfi.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Author: Lin Huang <hl@rock-chips.com> 8 #include <linux/devfreq-event.h> 63 void __iomem *dfi_regs = info->regs; in rockchip_dfi_start_hardware_counter() 68 regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); in rockchip_dfi_start_hardware_counter() 88 void __iomem *dfi_regs = info->regs; in rockchip_dfi_stop_hardware_counter() 98 void __iomem *dfi_regs = info->regs; in rockchip_dfi_get_busier_ch() 104 info->ch_usage[i].access = readl_relaxed(dfi_regs + in rockchip_dfi_get_busier_ch() 106 info->ch_usage[i].total = readl_relaxed(dfi_regs + in rockchip_dfi_get_busier_ch() 108 tmp = info->ch_usage[i].access; in rockchip_dfi_get_busier_ch() [all …]
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/openbmc/linux/drivers/clk/rockchip/ |
H A D | clk-rk3399.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Author: Xing Zheng <zhengxing@rock-chips.com> 7 #include <linux/clk-provider.h> 15 #include <dt-bindings/clock/rk3399-cru.h> 209 /* PMU CRU parents */ 402 * CRU Clock-Architecture 1254 * pclkin_cifinv --|-------\ 1255 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper 1256 * pclkin_cif --|-------/ 1302 /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */ [all …]
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/openbmc/u-boot/drivers/clk/rockchip/ |
H A D | clk_rk3399.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <clk-uclass.h> 10 #include <dt-structs.h> 20 #include <dt-bindings/clock/rk3399-cru.h> 41 ((input_rate) / (output_rate) - 1); 234 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 238 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 306 * FOUTVCO = Fractional PLL non-divided output frequency 317 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll() 318 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll() [all …]
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/openbmc/linux/drivers/pinctrl/ |
H A D | pinctrl-rockchip.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd. 8 * With some ideas taken from pinctrl-samsung: 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 198 RK3399, enumerator 242 * @offset: if initialized to -1 it will be autocalculated, by specifying 275 * @offset: if initialized to -1 it will be autocalculated, by specifying 373 * @route_location: the mux route location (same, pmu, grf).
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