Home
last modified time | relevance | path

Searched +full:rk3399 +full:- +full:pcie (Results 1 – 25 of 43) sorted by relevance

12

/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Drockchip,rk3399-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Endpoint
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
[all …]
H A Drockchip,rk3399-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Root Port Bridge Host
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
[all …]
H A Drockchip,rk3399-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Bridge Common Properties
10 - Shawn Lin <shawn.lin@rock-chips.com>
19 clock-names:
21 - const: aclk
22 - const: aclk-perf
23 - const: hclk
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drockchip-pcie-phy.txt1 Rockchip PCIE PHY
2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
14 - #phy-cells: must be 0
16 Required properties for per-lane PHY mode (preferred):
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-roc-pc-mezzanine.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
7 /dts-v1/;
8 #include "rk3399-roc-pc.dtsi"
11 model = "Firefly ROC-RK3399-PC Mezzanine Board";
12 compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
19 poe_12v: poe-12v {
20 compatible = "regulator-fixed";
21 regulator-name = "poe_12v";
22 regulator-always-on;
[all …]
H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
[all …]
H A Drk3399-ficus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
10 #include "rk3399-rock960.dtsi"
13 model = "96boards RK3399 Ficus";
14 compatible = "vamrs,ficus", "rockchip,rk3399";
17 stdout-path = "serial2:1500000n8";
20 clkin_gmac: external-gmac-clock {
21 compatible = "fixed-clock";
22 clock-frequency = <125000000>;
23 clock-output-names = "clkin_gmac";
[all …]
H A Drk3399-rock960.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3399-rock960.dtsi"
11 compatible = "vamrs,rock960", "rockchip,rk3399";
14 stdout-path = "serial2:1500000n8";
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>,
24 user_led1: led-1 {
27 linux,default-trigger = "heartbeat";
[all …]
H A Drk3399pro.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include "rk3399.dtsi"
10 /* Default to enabled since AP talk to NPU part over pcie */
15 /* Default to enabled since AP talk to NPU part over pcie */
17 ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
18 num-lanes = <4>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pcie_clkreqn_cpm>;
H A Drk3399-firefly.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/usb/pd.h>
11 #include "rk3399.dtsi"
12 #include "rk3399-opp.dtsi"
15 model = "Firefly-RK3399 Board";
16 compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
[all …]
H A Drk3399-kobol-helios64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 /dts-v1/;
14 #include "rk3399.dtsi"
15 #include "rk3399-opp.dtsi"
19 compatible = "kobol,helios64", "rockchip,rk3399";
29 avdd_0v9_s0: avdd-0v9-s0 {
30 compatible = "regulator-fixed";
31 regulator-name = "avdd_0v9_s0";
32 regulator-always-on;
33 regulator-boot-on;
[all …]
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
[all …]
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
9 #include "rk3399.dtsi"
10 #include "rk3399-op1-opp.dtsi"
19 stdout-path = "serial2:115200n8";
28 * - Rails that only connect to the EC (or devices that the EC talks to)
30 * - Rails _are_ included if the rails go to the AP even if the AP
39 * - The EC controls the enable and the EC always enables a rail as
41 * - The rails are actually connected to each other by a jumper and
[all …]
H A Drk3588s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-rock960.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
7 #include "rk3399-rock960.dtsi"
8 #include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
12 compatible = "vamrs,rock960", "rockchip,rk3399";
15 stdout-path = "serial2:1500000n8";
20 ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
24 pcie {
25 pcie_drv: pcie-drv {
32 host_vbus_drv: host-vbus-drv {
H A Drk3399-ficus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
10 #include "rk3399-rock960.dtsi"
11 #include "rk3399-sdram-ddr3-1600.dtsi"
14 model = "96boards RK3399 Ficus";
15 compatible = "vamrs,ficus", "rockchip,rk3399";
18 stdout-path = "serial2:1500000n8";
21 clkin_gmac: external-gmac-clock {
22 compatible = "fixed-clock";
23 clock-frequency = <125000000>;
[all …]
H A Drk3399.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd.
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,rk3399";
[all …]
H A Drk3399-firefly.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include "rk3399.dtsi"
10 #include "rk3399-sdram-ddr3-1600.dtsi"
13 model = "Firefly-RK3399 Board";
14 compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
17 stdout-path = &uart2;
18 u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
[all …]
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
9 #include "rk3399.dtsi"
10 #include "rk3399-op1-opp.dtsi"
14 u-boot,dm-pre-reloc;
15 stdout-path = "serial2:115200n8";
16 u-boot,spl-boot-order = &spi_flash;
20 u-boot,spl-payload-offset = <0x40000>;
29 * - Rails that only connect to the EC (or devices that the EC talks to)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
[all …]
/openbmc/linux/drivers/phy/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
19 associated to the Rockchip ISP module present in RK3399 SoCs.
22 will be called phy-rockchip-dphy-rx0.
74 Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
78 tristate "Rockchip PCIe PHY Driver"
84 Enable this to support the Rockchip PCIe PHY.
H A Dphy-rockchip-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip PCIe PHY driver
5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
23 * The higher 16-bit of this register is used for write protection
82 phys[inst->index]); in to_pcie_phy()
90 if (args->args_count == 0) in rockchip_pcie_phy_of_xlate()
91 return rk_phy->phys[0].phy; in rockchip_pcie_phy_of_xlate()
93 if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM)) in rockchip_pcie_phy_of_xlate()
94 return ERR_PTR(-ENODEV); in rockchip_pcie_phy_of_xlate()
96 return rk_phy->phys[args->args[0]].phy; in rockchip_pcie_phy_of_xlate()
[all …]
/openbmc/linux/drivers/pci/controller/dwc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
18 bool "Amazon Annapurna Labs PCIe controller"
24 Say Y here to enable support of the Amazon's Annapurna Labs PCIe
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
27 required only for DT-based platforms. ACPI platforms with the
28 Annapurna Labs PCIe controller don't need to enable this.
31 tristate "Amlogic Meson PCIe controller"
38 and therefore the driver re-uses the DesignWare core functions to
45 bool "Axis ARTPEC-6 PCIe controller (host mode)"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dsyscon.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
20 - Lee Jones <lee@kernel.org>
27 - syscon
30 - compatible
35 - items:
36 - enum:
[all …]
/openbmc/linux/drivers/pci/controller/
H A Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe endpoint controller driver
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
15 #include <linux/pci-epc.h>
17 #include <linux/pci-epf.h>
20 #include "pcie-rockchip.h"
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
24 * @rockchip: Rockchip PCIe controller
33 * IRQ) TLP through the PCIe bus.
[all …]

12