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/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3368.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,rk3368";
[all …]
H A Drk3368-px5-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3368.dtsi"
8 #include <dt-bindings/input/input.h>
12 compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
20 stdout-path = "serial4:115200n8";
28 keys: gpio-keys {
29 compatible = "gpio-keys";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pwr_key>;
[all …]
H A Drk3368-geekbox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3368.dtsi"
8 #include <dt-bindings/input/input.h>
12 compatible = "geekbuying,geekbox", "rockchip,rk3368";
19 stdout-path = "serial2:115200n8";
27 ext_gmac: gmac-clk {
28 compatible = "fixed-clock";
29 clock-frequency = <125000000>;
30 clock-output-names = "ext_gmac";
[all …]
H A Drk3368-r88.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3368.dtsi"
8 #include <dt-bindings/input/input.h>
12 compatible = "rockchip,r88", "rockchip,rk3368";
20 stdout-path = "serial2:115200n8";
28 emmc_pwrseq: emmc-pwrseq {
29 compatible = "mmc-pwrseq-emmc";
30 pinctrl-0 = <&emmc_reset>;
31 pinctrl-names = "default";
[all …]
H A Drk3368-orion-r68-meta.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
8 #include "rk3368.dtsi"
12 compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
20 stdout-path = "serial2:115200n8";
28 emmc_pwrseq: emmc-pwrseq {
29 compatible = "mmc-pwrseq-emmc";
30 pinctrl-0 = <&emmc_reset>;
31 pinctrl-names = "default";
[all …]
H A Drk3368-lion.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3368.dtsi"
15 stdout-path = "serial0:115200n8";
18 ext_gmac: gmac-clk {
19 compatible = "fixed-clock";
20 clock-frequency = <125000000>;
21 clock-output-names = "ext_gmac";
22 #clock-cells = <0>;
26 compatible = "i2c-mux-gpio";
[all …]
H A Drk3368-evb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2015 Caesar Wang <wxt@rock-chips.com>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pwm/pwm.h>
8 #include "rk3368.dtsi"
16 stdout-path = "serial2:115200n8";
25 compatible = "pwm-backlight";
26 brightness-levels = <
59 default-brightness-level = <128>;
60 enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
[all …]
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Drockchip-io-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip-io-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
29 should have power or not have power
42 to report their voltage. The IO Voltage Domain for any non-specified
48 - rockchip,px30-io-voltage-domain
49 - rockchip,px30-pmu-io-voltage-domain
50 - rockchip,rk3188-io-voltage-domain
[all …]
H A Drockchip,power-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Power Domains
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 Rockchip processors include support for multiple power domains
16 application scenarios to save power.
18 Power domains contained within power-controller node are
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3368-lion.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
6 /dts-v1/;
7 #include "rk3368.dtsi"
8 #include "rk3368-lion-u-boot.dtsi"
9 #include <dt-bindings/input/input.h>
12 model = "Theobroma Systems RK3368-uQ7 SoM";
13 compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368";
25 ext_gmac: gmac-clk {
26 compatible = "fixed-clock";
27 clock-frequency = <125000000>;
[all …]
H A Drk3368-sheep.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
7 #include "rk3368.dtsi"
8 #include <dt-bindings/input/input.h>
12 compatible = "rockchip,sheep", "rockchip,rk3368";
15 stdout-path = "serial2:115200n8";
23 ext_gmac: gmac-clk {
24 compatible = "fixed-clock";
25 clock-frequency = <125000000>;
26 clock-output-names = "ext_gmac";
[all …]
H A Drk3368-px5-evb.dts4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "rk3368.dtsi"
45 #include <dt-bindings/input/input.h>
49 compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
52 stdout-path = "serial4:115200n8";
60 ext_gmac: gmac-clk {
61 compatible = "fixed-clock";
62 clock-frequency = <125000000>;
63 clock-output-names = "ext_gmac";
[all …]
H A Drk3368-geekbox.dts4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "rk3368.dtsi"
45 #include <dt-bindings/input/input.h>
49 compatible = "geekbuying,geekbox", "rockchip,rk3368";
52 stdout-path = "serial2:115200n8";
60 ext_gmac: gmac-clk {
61 compatible = "fixed-clock";
62 clock-frequency = <125000000>;
63 clock-output-names = "ext_gmac";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/rockchip/
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Power Management Unit (PMU)
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The PMU is used to turn on and off different power domains of the SoCs.
15 This includes the power to the CPU cores.
22 - rockchip,px30-pmu
23 - rockchip,rk3066-pmu
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drockchip-inno-csi-dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Heiko Stuebner <heiko@sntech.de>
13 The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
19 - rockchip,px30-csi-dphy
20 - rockchip,rk1808-csi-dphy
21 - rockchip,rk3326-csi-dphy
[all …]
H A Drockchip,px30-dsi-dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
13 "#phy-cells":
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
21 - rockchip,rk3568-dsi-dphy
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,px30-vop-big
22 - rockchip,px30-vop-lit
23 - rockchip,rk3036-vop
24 - rockchip,rk3066-vop
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Drockchip-spdif.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Heiko Stuebner <heiko@sntech.de>
20 - const: rockchip,rk3066-spdif
21 - const: rockchip,rk3228-spdif
22 - const: rockchip,rk3328-spdif
23 - const: rockchip,rk3366-spdif
24 - const: rockchip,rk3368-spdif
[all …]
H A Drockchip-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The I2S bus (Inter-IC sound bus) is a serial link for digital
14 - Heiko Stuebner <heiko@sntech.de>
17 - $ref: dai-common.yaml#
22 - const: rockchip,rk3066-i2s
23 - items:
24 - enum:
[all …]
/openbmc/u-boot/board/rockchip/sheep_rk3368/
H A DREADME1 Here is the step-by-step to boot to U-Boot on rk3368.
3 Get miniloader and trust.img form rockchip vendor u-boot source code
5 > git clone https://github.com/rockchip-linux/u-boot.git rockchip-uboot
6 > cd rockchip-uboot
10 Compile the upstream U-Boot
12 > cd u-boot
13 > make CROSS_COMPILE=aarch64-linux-gnu- sheep-rk3368_defconfig all
15 Package u-boot for miniloader
17 > ../rockchip-uboot/tools/loaderimage --pack --uboot u-boot.bin u-boot.img
21 rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git
[all …]
/openbmc/u-boot/drivers/ram/rockchip/
H A Ddmc-rk3368.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/memory/rk3368-dmc.h>
10 #include <dt-structs.h>
123 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
125 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
133 (((n - 5) & 0x7) << 3)
141 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
143 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
149 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
151 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
[all …]
/openbmc/u-boot/doc/
H A DREADME.rockchip1 # SPDX-License-Identifier: GPL-2.0+
6 U-Boot on Rockchip
9 A wide range of Rockchip SoCs are supported in mainline U-Boot
17 - Firefly RK3288 board or something else with a supported RockChip SoC
18 - Power connection to 5V using the supplied micro-USB power cable
19 - Separate USB serial cable attached to your computer and the Firefly
20 (connect to the micro-USB connector below the logo)
21 - rkflashtool [3]
22 - openssl (sudo apt-get install openssl)
23 - Serial UART connection [4]
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: spi-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rk3036-spi
24 - const: rockchip,rk3066-spi
25 - const: rockchip,rk3228-spi
26 - const: rockchip,rv1108-spi
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Drockchip-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 controller that are not already included in the synopsys-dw-mshc-common.yaml
17 - $ref: synopsys-dw-mshc-common.yaml#
20 - Heiko Stuebner <heiko@sntech.de>
27 - const: rockchip,rk2928-dw-mshc
29 - const: rockchip,rk3288-dw-mshc
30 - items:
[all …]

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