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/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
[all …]
H A Drk3288-evb-rk808.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include "rk3288-evb.dtsi"
7 model = "Rockchip RK3288 EVB RK808";
8 compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
12 clock-frequency = <400000>;
17 interrupt-parent = <&gpio0>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pmic_int &global_pwroff>;
21 rockchip,system-power-controller;
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H A Drk3288-firefly-reload.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device tree file for Firefly Rockchip RK3288 Core board
7 /dts-v1/;
8 #include "rk3288-firefly-reload-core.dtsi"
11 model = "Firefly-RK3288-reload";
12 compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
14 adc-keys {
15 compatible = "adc-keys";
16 io-channels = <&saradc 1>;
17 io-channel-names = "buttons";
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H A Drk3288-veyron-pinky.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "../cros-ec-sbs.dtsi"
14 compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
15 "google,veyron", "rockchip,rk3288";
17 /delete-node/backlight-regulator;
18 /delete-node/panel-regulator;
19 /delete-node/emmc-pwrseq;
20 /delete-node/vcc18-lcd;
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H A Drk3288-veyron-brain.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron.dtsi"
10 #include "rk3288-veyron-broadcom-bluetooth.dtsi"
14 compatible = "google,veyron-brain-rev0", "google,veyron-brain",
15 "google,veyron", "rockchip,rk3288";
17 vcc33_sys: vcc33-sys {
18 vin-supply = <&vcc_5v>;
22 compatible = "regulator-fixed";
23 regulator-name = "vcc33_io";
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/openbmc/u-boot/arch/arm/dts/
H A Drk3288.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power-domain/rk3288.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/video/rk3288.h>
14 compatible = "rockchip,rk3288";
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H A Drk3288-firefly.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
6 /dts-v1/;
7 #include "rk3288-firefly.dtsi"
10 model = "Firefly-RK3288";
11 compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
14 stdout-path = &uart2;
18 u-boot,dm-pre-reloc;
19 u-boot,boot-led = "firefly:green:power";
24 rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
29 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
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H A Drk3288-veyron-speedy.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "cros-ec-sbs.dtsi"
11 #include "rk3288-veyron-speedy-u-boot.dtsi"
15 compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
16 "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
17 "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
18 "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
19 "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
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/openbmc/u-boot/arch/arm/mach-rockchip/rk3288/
H A DKconfig4 bool "Google/Rockchip Veyron-Jerry Chromebook"
7 Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
8 HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
9 WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
13 bool "Google/Rockchip Veyron-Mickey Chromebit"
16 Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
17 and WiFi. It has a separate power port and is designed to connect
23 bool "Google/Rockchip Veyron-Minnie Chromebook"
26 Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
27 ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Drockchip-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/rockchip-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ezequiel Garcia <ezequiel@collabora.com>
19 - enum:
20 - rockchip,rk3036-vpu
21 - rockchip,rk3066-vpu
22 - rockchip,rk3288-vpu
23 - rockchip,rk3328-vpu
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H A Drockchip-rga.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-rga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Jacob Chen <jacob-chen@iotwrt.com>
16 - Ezequiel Garcia <ezequiel@collabora.com>
21 - const: rockchip,rk3288-rga
22 - const: rockchip,rk3399-rga
23 - items:
24 - enum:
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/openbmc/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
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/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
21 - rockchip,px30-vop-big
22 - rockchip,px30-vop-lit
23 - rockchip,rk3036-vop
24 - rockchip,rk3066-vop
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H A Drockchip,lvds.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip low-voltage differential signal (LVDS) transmitter
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - rockchip,px30-lvds
17 - rockchip,rk3288-lvds
25 clock-names:
28 avdd1v0-supply:
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H A Drockchip,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - enum:
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3288-mipi-dsi
19 - rockchip,rk3399-mipi-dsi
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H A Drockchip,analogix-dp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - rockchip,rk3288-dp
17 - rockchip,rk3399-edp
23 clock-names:
26 - const: dp
[all …]
/openbmc/linux/drivers/soc/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 special additional settings registers for a lot of soc-components.
26 bool "Rockchip generic power domain"
30 Say y here to enable power domain support.
31 In order to meet high performance and low power requirements, a power
32 management unit is designed or saving power when RK3288 in low power
33 mode. The RK3288 PMU is dedicated for managing the power of the whole chip.
41 Describe the hierarchy for the Dynamic Thermal Power Management tree
42 on this platform. That will create all the power capping capable
/openbmc/u-boot/doc/
H A DREADME.rockchip1 # SPDX-License-Identifier: GPL-2.0+
6 U-Boot on Rockchip
9 A wide range of Rockchip SoCs are supported in mainline U-Boot
17 - Firefly RK3288 board or something else with a supported RockChip SoC
18 - Power connection to 5V using the supplied micro-USB power cable
19 - Separate USB serial cable attached to your computer and the Firefly
20 (connect to the micro-USB connector below the logo)
21 - rkflashtool [3]
22 - openssl (sudo apt-get install openssl)
23 - Serial UART connection [4]
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/openbmc/linux/Documentation/devicetree/bindings/arm/rockchip/
H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Power Management Unit (PMU)
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The PMU is used to turn on and off different power domains of the SoCs.
15 This includes the power to the CPU cores.
22 - rockchip,px30-pmu
23 - rockchip,rk3066-pmu
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Drockchip-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 controller that are not already included in the synopsys-dw-mshc-common.yaml
17 - $ref: synopsys-dw-mshc-common.yaml#
20 - Heiko Stuebner <heiko@sntech.de>
26 # for Rockchip RK2928 and before RK3288
27 - const: rockchip,rk2928-dw-mshc
28 # for Rockchip RK3288
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Drockchip,rk3288-hdmi-analog.txt1 ROCKCHIP RK3288 with HDMI and analog audio
4 - compatible: "rockchip,rk3288-hdmi-analog"
5 - rockchip,model: The user-visible name of this sound complex
6 - rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
8 - rockchip,audio-codec: The phandle of the analog audio codec.
9 - rockchip,routing: A list of the connections between audio components.
16 - rockchip,hp-en-gpios = The phandle of the GPIO that power up/down the
18 - rockchip,hp-det-gpios = The phandle of the GPIO that detects the headphone
20 - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
25 compatible = "rockchip,rk3288-hdmi-analog";
[all …]
H A Drockchip-spdif.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Heiko Stuebner <heiko@sntech.de>
20 - const: rockchip,rk3066-spdif
21 - const: rockchip,rk3228-spdif
22 - const: rockchip,rk3328-spdif
23 - const: rockchip,rk3366-spdif
24 - const: rockchip,rk3368-spdif
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3368.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Drockchip-io-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip-io-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
17 A specific example using rk3288
29 should have power or not have power
42 to report their voltage. The IO Voltage Domain for any non-specified
48 - rockchip,px30-io-voltage-domain
49 - rockchip,px30-pmu-io-voltage-domain
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/
H A Drk3288-board-spl.c1 // SPDX-License-Identifier: GPL-2.0+
30 #include <power/regulator.h>
31 #include <power/rk8xx_pmic.h>
38 const void *blob = gd->fdt_blob; in spl_boot_device()
44 bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); in spl_boot_device()
60 debug("Found device %s\n", dev->name); in spl_boot_device()
112 /* Example code showing how to enable the debug UART on RK3288 */ in board_init_f()
114 /* Enable early UART on the RK3288 */ in board_init_f()
118 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | in board_init_f()
148 if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { in board_init_f()
[all …]

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