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/openbmc/qemu/docs/specs/
H A Driscv-iommu.rst1 .. _riscv-iommu:
3 RISC-V IOMMU support for RISC-V machines
6 QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
9 The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU
10 RISC-V boards can use. The 'virt' RISC-V machine is compatible with this
13 riscv-iommu-pci reference device
14 --------------------------------
16 This device implements the RISC-V IOMMU emulation as recommended by the section
18 class 08h, sub-class 06h and programming interface 00h.
25 .. code-block:: bash
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/openbmc/linux/arch/riscv/
H A DMakefile2 # architecture-specific flags and dependencies.
9 LDFLAGS_vmlinux := -z norelro
11 LDFLAGS_vmlinux += -shared -Bsymbolic -z notext --emit-relocs
12 KBUILD_CFLAGS += -fPIE
15 LDFLAGS_vmlinux += --no-relax
16 KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
18 CC_FLAGS_FTRACE := -fpatchable-function-entry=4
20 CC_FLAGS_FTRACE := -fpatchable-function-entry=2
25 KBUILD_CFLAGS_MODULE += -mcmodel=medany
33 KBUILD_CFLAGS += -mabi=lp64
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
13 config RISCV config
169 # https://github.com/llvm/llvm-project/commit/6ab8927931851bb42b2c93a00801dc499d7d9b1e
176 depends on $(cc-option,-fpatchable-function-entry=8)
186 # VA_BITS - PAGE_SHIFT - 3
199 # set if we are running in S-mode and can use SBI calls
206 bool "MMU-based Paged Memory Management Support"
209 Select if you want MMU-based virtualised addressing space
286 This enables function pointer support for non-standard noncoherent
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/openbmc/qemu/include/semihosting/
H A Dcommon-semi.h3 * semihosting syscalls design. This includes Arm and RISC-V processors
10 * Adapted for systems other than ARM, including RISC-V, by Keith Packard
29 * RISC-V Semihosting is documented in:
30 * RISC-V Semihosting
31 * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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/openbmc/qemu/hw/riscv/
H A Driscv-iommu-pci.c2 * QEMU emulation of an RISC-V IOMMU
4 * Copyright (C) 2022-2023 Rivos Inc.
23 #include "hw/qdev-properties.h"
24 #include "hw/riscv/riscv_hart.h"
27 #include "qemu/error-report.h"
28 #include "qemu/host-utils.h"
32 #include "riscv-iommu.h"
33 #include "riscv-iommu-bits.h"
35 /* RISC-V IOMMU PCI Device Emulation */
39 * 4 MSIx vectors for ICVEC, one for MRIF. The spec mentions in
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H A Dvirt-acpi-build.c4 * RISC-V virt ACPI generation
6 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
10 * Copyright (C) 2021-2023 Ventana Micro Systems Inc
27 #include "hw/acpi/acpi-defs.h"
29 #include "hw/acpi/aml-build.h"
34 #include "hw/pci-host/gpex.h"
35 #include "hw/riscv/virt.h"
36 #include "hw/riscv/numa.h"
37 #include "hw/virtio/virtio-acpi.h"
40 #include "qemu/error-report.h"
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H A Driscv-iommu-bits.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2023 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
5 * Copyright © 2023 RISC-V IOMMU Task Group
7 * RISC-V IOMMU - Register Layout and Data Structures.
9 * Based on the IOMMU spec version 1.0, 3/2023
10 * https://github.com/riscv-non-isa/riscv-iommu
19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
23 * struct riscv_iommu_fq_record - Fault/Event Queue Record
40 * struct riscv_iommu_pq_record - PCIe Page Request record
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H A Driscv-iommu.c2 * QEMU emulation of an RISC-V IOMMU
4 * Copyright (C) 2021-2023, Rivos Inc.
23 #include "hw/qdev-properties.h"
24 #include "hw/riscv/riscv_hart.h"
30 #include "riscv-iommu.h"
31 #include "riscv-iommu-bits.h"
60 uint64_t satp; /* S-Stage address translation and protection */
61 uint64_t gatp; /* G-Stage address translation and protection */
62 uint64_t msi_addr_mask; /* MSI filtering - address mask */
63 uint64_t msi_addr_pattern; /* MSI filtering - address pattern */
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/openbmc/linux/Documentation/riscv/
H A Dvector.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
11 ---------------------
15 these interfaces is to give init systems a way to modify the availability of V
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
20 to use in a portable code. To get the availability of V in an ELF program,
27 argument consists of two 2-bit enablement statuses and a bit for inheritance
30 Enablement status is a tri-state value each occupying 2-bit of space in
33 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
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/openbmc/qemu/tests/qtest/
H A Driscv-iommu-test.c2 * QTest testcase for RISC-V IOMMU
7 * option) any later version. See the COPYING file in the top-level directory.
12 #include "libqtest-single.h"
15 #include "libqos/riscv-iommu.h"
20 return qpci_io_readl(&r_iommu->dev, r_iommu->reg_bar, reg_offset); in riscv_iommu_read_reg32()
25 return qpci_io_readq(&r_iommu->dev, r_iommu->reg_bar, reg_offset); in riscv_iommu_read_reg64()
31 qpci_io_writel(&r_iommu->dev, r_iommu->reg_bar, reg_offset, val); in riscv_iommu_write_reg32()
37 qpci_io_writeq(&r_iommu->dev, r_iommu->reg_bar, reg_offset, val); in riscv_iommu_write_reg64()
43 QPCIDevice *dev = &r_iommu->dev; in test_pci_config()
92 * Common timeout-based poll for CQCSR, FQCSR and PQCSR. All
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/openbmc/linux/arch/riscv/kernel/
H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include "copy-unaligned.h"
29 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
33 #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
40 /* Per-cpu ISA extensions. */
47 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
88 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_isa_extension_check()
91 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_isa_extension_check()
97 pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n"); in riscv_isa_extension_check()
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H A Dacpi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V Specific Low-Level ACPI Boot Support
5 * Copyright (C) 2013-2014, Linaro Ltd.
12 * Copyright (C) 2021-2023, Ventana Micro Systems Inc.
13 * Author: Sunil V L <sunilvl@ventanamicro.com>
37 return -EINVAL; in parse_acpi()
47 return -EINVAL; /* Core will print when we return error */ in parse_acpi()
54 * acpi_fadt_sanity_check() - Check FADT presence and carry out sanity
67 * FADT is required on riscv; retrieve it to check its presence in acpi_fadt_sanity_check()
75 return -ENODEV; in acpi_fadt_sanity_check()
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/openbmc/u-boot/drivers/timer/
H A DKconfig9 will be used. The timer is usually a 32 bits free-running up
31 bool "Allow timer to be used early in U-Boot"
38 active. Examples include when using CONFIG_TRACE to trace U-Boot's
60 Select this to enable built-in ARC timers.
61 ARC cores may have up to 2 built-in timers: timer0 and timer1,
63 in U-Boot.
130 bool "RISC-V timer support"
131 depends on TIMER && RISCV
134 by the RISC-V privileged architecture spec.
165 bool "x86 Time-Stamp Counter (TSC) timer support"
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/openbmc/qemu/hw/intc/
H A Driscv_aclint.c2 * RISC-V ACLINT (Advanced Core Local Interruptor)
3 * URL: https://github.com/riscv/riscv-aclint
5 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
9 * This provides real-time clock, timer and interprocessor interrupts.
26 #include "qemu/error-report.h"
30 #include "target/riscv/cpu.h"
31 #include "hw/qdev-properties.h"
51 return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta; in cpu_riscv_read_rtc()
63 uint32_t timebase_freq = mtimer->timebase_freq; in riscv_aclint_mtimer_write_timecmp()
70 hartid = hartid - mtimer->hartid_base; in riscv_aclint_mtimer_write_timecmp()
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/openbmc/qemu/semihosting/
H A Darm-compat-semi.c3 * semihosting syscalls design. This includes Arm and RISC-V processors
10 * Adapted for systems other than ARM, including RISC-V, by Keith Packard
27 * https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst
29 * RISC-V Semihosting is documented in:
30 * RISC-V Semihosting
31 * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
40 #include "semihosting/common-semi.h"
130 if (!mr->ram || mr->readonly) { in find_ram_cb()
134 if (size > info->ramsize) { in find_ram_cb()
135 info->rambase = int128_get64(start); in find_ram_cb()
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/openbmc/qemu/target/riscv/
H A Dcpu.c2 * QEMU RISC-V CPU
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
21 #include "qemu/qemu-print.h"
27 #include "exec/exec-all.h"
30 #include "qemu/error-report.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/core/qdev-prop-internal.h"
34 #include "fpu/softfloat-helpers.h"
39 #include "tcg/tcg-cpu.h"
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H A Dcpu.h2 * QEMU RISC-V CPU
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
25 #include "hw/qdev-properties.h"
26 #include "exec/cpu-defs.h"
28 #include "qemu/cpu-float.h"
33 #include "qapi/qapi-types-common.h"
34 #include "cpu-qom.h"
47 * RISC-V-specific extra insn start words:
57 #define RV(x) ((target_ulong)1 << (x - 'A'))
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H A Ddebug.c2 * QEMU RISC-V Native Debug Support
10 * in the RISC-V Debug Specification:
11 * https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
31 #include "exec/exec-all.h"
32 #include "exec/helper-proto.h"
33 #include "sysemu/cpu-timers.h"
36 * The following M-mode trigger CSRs are implemented:
38 * - tselect
39 * - tdata1
40 * - tdata2
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H A Dvector_helper.c2 * RISC-V Vector Extension Helpers for QEMU.
4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
20 #include "qemu/host-utils.h"
24 #include "exec/exec-all.h"
26 #include "exec/page-protection.h"
27 #include "exec/helper-proto.h"
29 #include "tcg/tcg-gvec-desc.h"
44 bool vill = (s2 >> (xlen - 1)) & 0x1; in HELPER()
47 xlen - 1 - R_VTYPE_RESERVED_SHIFT); in HELPER()
48 uint16_t vlen = cpu->cfg.vlenb << 3; in HELPER()
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/openbmc/linux/drivers/irqchip/
H A Dirq-sifive-plic.c1 // SPDX-License-Identifier: GPL-2.0
24 * This driver implements a version of the RISC-V PLIC with the actual layout
27 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
29 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
30 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
31 * Spec.
106 raw_spin_lock(&handler->enable_lock); in plic_toggle()
107 __plic_toggle(handler->enable_base, hwirq, enable); in plic_toggle()
108 raw_spin_unlock(&handler->enable_lock); in plic_toggle()
119 plic_toggle(handler, d->hwirq, enable); in plic_irq_toggle()
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/openbmc/qemu/docs/about/
H A Demulation.rst9 .. list-table:: Supported Guest Architectures for Emulation
11 :header-rows: 1
13 * - Architecture (qemu name)
14 - System
15 - User
16 - Notes
17 * - Alpha
18 - Yes
19 - Yes
20 - Legacy 64 bit RISC ISA developed by DEC
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/openbmc/qemu/
H A DMAINTAINERS10 consult qemu-devel and not any specific individual privately.
23 W: Web-page with status/info
59 ------------------------------
63 L: qemu-devel@nongnu.org
72 R: Philippe Mathieu-Daudé <philmd@linaro.org>
76 F: docs/devel/code-of-conduct.rst
77 F: docs/devel/conflict-resolution.rst
78 F: docs/devel/submitting-a-patch.rst
79 F: docs/devel/submitting-a-pull-request.rst
82 -------------------------------------------------
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/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c2 * riscv TCG cpu class initialization
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
21 #include "exec/exec-all.h"
22 #include "tcg-cpu.h"
30 #include "qemu/error-report.h"
32 #include "hw/core/accel-cpu.h"
33 #include "hw/core/tcg-cpu-ops.h"
73 CPURISCVState *env = &cpu->env; in riscv_cpu_write_misa_bit()
76 env->misa_ext |= bit; in riscv_cpu_write_misa_bit()
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