/openbmc/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-j721e-evm-gesi-exp-board.dtso | 1 // SPDX-License-Identifier: GPL-2.0 3 * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with 8 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 11 /dts-v1/; 14 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/net/ti-dp83867.h> 17 #include "k3-pinctrl.h" 21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; 22 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; 23 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; [all …]
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H A D | k3-j721s2-evm-gesi-exp-board.dtso | 1 // SPDX-License-Identifier: GPL-2.0 7 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 10 /dts-v1/; 13 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/net/ti-dp83867.h> 16 #include "k3-pinctrl.h" 20 ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; 25 main_cpsw_mdio_default_pins: main-cpsw-mdio-default-pins { 26 pinctrl-single,pins = < 32 rgmii1_default_pins: rgmii1-default-pins { [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - David S. Miller <davem@davemloft.net> 20 local-mac-address: 23 $ref: /schemas/types.yaml#/definitions/uint8-array 27 mac-address: 32 local-mac-address property. 33 $ref: /schemas/types.yaml#/definitions/uint8-array [all …]
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H A D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+ 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Alexandru Tachici <alexandru.tachici@analog.com> 16 - $ref: ethernet-phy.yaml# 19 adi,rx-internal-delay-ps: 21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with 22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. 26 adi,tx-internal-delay-ps: 28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with [all …]
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H A D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Sae <frank.sae@motor-comm.com> 13 - $ref: ethernet-phy.yaml# 18 - ethernet-phy-id4f51.e91a 19 - ethernet-phy-id4f51.e91b 21 rx-internal-delay-ps: 23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with 24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. [all …]
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H A D | mediatek-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Biao Huang <biao.huang@mediatek.com> 21 - mediatek,mt2712-gmac 22 - mediatek,mt8188-gmac 23 - mediatek,mt8195-gmac 25 - compatible 28 - $ref: snps,dwmac.yaml# [all …]
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/openbmc/u-boot/doc/device-tree-bindings/net/ |
H A D | ethernet.txt | 3 - local-mac-address: array of 6 bytes, specifies the MAC address that was 5 - mac-address: array of 6 bytes, specifies the MAC address that was last used by 7 the device by the boot program is different from the "local-mac-address" 9 - max-speed: number, specifies maximum speed in Mbit/s supported by the device; 10 - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than 12 - phy-mode: string, operation mode of the PHY interface; supported values are 13 "mii", "gmii", "sgmii", "qsgmii", "tbi", "rev-mii", "rmii", "rgmii", "rgmii-id", 14 "rgmii-rxid", "rgmii-txid", "rtbi", "smii", "xgmii"; this is now a de-facto 16 - phy-connection-type: the same as "phy-mode" property but described in ePAPR; 17 - phy-handle: phandle, specifies a reference to a node representing a PHY [all …]
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H A D | fsl-tsec-phy.txt | 1 * TSEC-compatible ethernet nodes 5 - compatible : Should be "fsl,tsec" 6 - reg : Offset and length of the register set for the device 7 - phy-handle : See ethernet.txt file in the same directory. 8 - phy-connection-type : See ethernet.txt file in the same directory. This 9 property is only really needed if the connection is of type "rgmii-id", 10 "rgmii-rxid" and "rgmii-txid" as all other connection types are detected 17 phy-handle = <&phy0>; 18 phy-connection-type = "sgmii"; 30 - compatible : Should define the compatible device type for the [all …]
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/openbmc/u-boot/include/ |
H A D | phy_interface.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 44 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", 48 [PHY_INTERFACE_MODE_RGMII] = "rgmii", 49 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", 50 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", 51 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", 58 [PHY_INTERFACE_MODE_25G_AUI] = "25g-aui", 62 [PHY_INTERFACE_MODE_NCSI] = "NC-SI",
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/openbmc/linux/Documentation/ABI/testing/ |
H A D | sysfs-class-net-phydev | 24 This attribute contains the 32-bit PHY Identifier as reported 41 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii, 42 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii 43 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui, 44 xaui, 10gbase-kr, unknown 60 32-bit hexadecimal number representing a bit mask of the
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/openbmc/u-boot/arch/arm/dts/ |
H A D | ast2600-pfr.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /dts-v1/; 4 #include "ast2600-u-boot.dtsi" 8 compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; 16 stdout-path = &uart5; 34 clock-frequency = <800000000>; 37 clock-frequency = <800000000>; 43 u-boot,dm-pre-reloc; 48 clock-frequency = <400000000>; 65 pinctrl-names = "default"; [all …]
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H A D | ast2600-evb.dts | 1 /dts-v1/; 3 #include "ast2600-u-boot.dtsi" 7 compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; 15 stdout-path = &uart5; 33 clock-frequency = <800000000>; 36 clock-frequency = <800000000>; 42 u-boot,dm-pre-reloc; 47 clock-frequency = <400000000>; 64 pinctrl-names = "default"; 65 pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default [all …]
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H A D | ast2600-ampere.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 /dts-v1/; 5 #include "ast2600-u-boot.dtsi" 9 compatible = "aspeed,ast2600-ampere", "aspeed,ast2600"; 17 stdout-path = &uart5; 27 clock-frequency = <800000000>; 30 clock-frequency = <800000000>; 36 u-boot,dm-pre-reloc; 41 clock-frequency = <400000000>; 58 pinctrl-names = "default"; [all …]
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/openbmc/linux/arch/arm/boot/dts/aspeed/ |
H A D | aspeed-ast2600-evb.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 /dts-v1/; 6 #include "aspeed-g6.dtsi" 7 #include <dt-bindings/gpio/aspeed-gpio.h> 11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600"; 26 reserved-memory { 27 #address-cells = <1>; 28 #size-cells = <1>; 34 compatible = "shared-dma-pool"; 41 compatible = "shared-dma-pool"; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/dsa/ |
H A D | microchip,lan937x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - UNGLinuxDriver@microchip.com 13 - $ref: dsa.yaml#/$defs/ethernet-ports 18 - microchip,lan9370 19 - microchip,lan9371 20 - microchip,lan9372 21 - microchip,lan9373 22 - microchip,lan9374 [all …]
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H A D | nxp,sja1105.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at 16 - Vladimir Oltean <vladimir.oltean@nxp.com> 21 - nxp,sja1105e 22 - nxp,sja1105t 23 - nxp,sja1105p 24 - nxp,sja1105q 25 - nxp,sja1105r [all …]
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/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
H A D | ucc.txt | 4 - device_type : should be "network", "hldc", "uart", "transparent" 6 - compatible : could be "ucc_geth" or "fsl_atm" and so on. 7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM. 8 - reg : Offset and length of the register set for the device 9 - interrupts : <a b> where a is the interrupt number and b is a 14 - pio-handle : The phandle for the Parallel I/O port configuration. 15 - port-number : for UART drivers, the port number to use, between 0 and 3. 18 CPM UART driver, the port-number is required for the QE UART driver. 19 - soft-uart : for UART drivers, if specified this means the QE UART device 20 driver should use "Soft-UART" mode, which is needed on some SOCs that have [all …]
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/openbmc/linux/arch/arm64/boot/dts/allwinner/ |
H A D | sun50i-h618-orangepi-zero3.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 8 #include "sun50i-h616-orangepi-zero.dtsi" 12 compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; 16 allwinner,tx-delay-ps = <700>; 17 phy-mode = "rgmii-rxid"; 18 phy-supply = <®_dldo1>; 22 motorcomm,clk-out-frequency-hz = <125000000>; 30 broken-cd; 31 vmmc-supply = <®_dldo1>; [all …]
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/openbmc/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm2711-rpi-cm4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "bcm2711-rpi.dtsi" 5 #include "bcm283x-rpi-wifi-bt.dtsi" 8 compatible = "raspberrypi,4-compute-module", "brcm,bcm2711"; 12 stdout-path = "serial1:115200n8"; 15 sd_io_1v8_reg: regulator-sd-io-1v8 { 16 compatible = "regulator-gpio"; 17 regulator-name = "vdd-sd-io"; 18 regulator-min-microvolt = <1800000>; [all …]
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H A D | bcm2711-rpi-4-b.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include "bcm2711-rpi.dtsi" 5 #include "bcm283x-rpi-led-deprecated.dtsi" 6 #include "bcm283x-rpi-usb-peripheral.dtsi" 7 #include "bcm283x-rpi-wifi-bt.dtsi" 10 compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; 15 stdout-path = "serial1:115200n8"; 18 sd_io_1v8_reg: regulator-sd-io-1v8 { 19 compatible = "regulator-gpio"; [all …]
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/openbmc/linux/arch/mips/boot/dts/ralink/ |
H A D | mt7621-gnubee-gb-pc2.dts | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 /dts-v1/; 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/input/input.h> 10 compatible = "gnubee,gb-pc2", "mediatek,mt7621-soc"; 11 model = "GB-PC2"; 23 gpio-keys { 24 compatible = "gpio-keys"; 26 key-reset { 33 gpio-leds { [all …]
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/openbmc/u-boot/drivers/net/phy/ |
H A D | realtek.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc. 18 /* RTL8211x 1000BASE-T Control Register */ 91 phydev->flags |= PHY_RTL8211x_FORCE_MASTER; in rtl8211b_probe() 100 phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX; in rtl8211e_probe() 117 if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) { in rtl8211x_config() 127 if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) { in rtl8211x_config() 161 /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */ in rtl8211f_config() 162 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in rtl8211f_config() 163 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in rtl8211f_config() [all …]
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H A D | vitesse.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright 2010-2014 Freescale Semiconductor, Inc. 7 * Add vsc8662 phy support - Priyanka Jain 93 phydev->duplex = DUPLEX_FULL; in vitesse_parse_status() 95 phydev->duplex = DUPLEX_HALF; in vitesse_parse_status() 100 phydev->speed = SPEED_1000; in vitesse_parse_status() 103 phydev->speed = SPEED_100; in vitesse_parse_status() 106 phydev->speed = SPEED_10; in vitesse_parse_status() 144 * applied to "rgmii-id" interfaces. It may not work as expected 145 * on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */ [all …]
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/openbmc/linux/arch/powerpc/boot/dts/ |
H A D | mpc836x_rdk.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 * Copyright 2007-2008 MontaVista Software, Inc. 11 /dts-v1/; 14 #address-cells = <1>; 15 #size-cells = <1>; 31 #address-cells = <1>; 32 #size-cells = <0>; 37 d-cache-line-size = <32>; 38 i-cache-line-size = <32>; 39 d-cache-size = <32768>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt2712-evb.dts | 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 14 chassis-type = "embedded"; 15 compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; 27 stdout-path = "serial0:921600n8"; 30 cpus_fixed_vproc0: regulator-vproc-buck0 { 31 compatible = "regulator-fixed"; 32 regulator-name = "vproc_buck0"; 33 regulator-min-microvolt = <1000000>; [all …]
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