Home
last modified time | relevance | path

Searched +full:reset +full:- +full:post +full:- +full:delay +full:- +full:us (Results 1 – 25 of 252) sorted by relevance

1234567891011

/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
[all …]
H A Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
[all …]
H A Dhisilicon-hix5hd2-gmac.txt4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 of common properties between various SOC designs. It thus enables us to use
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-crd-r3.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include "sc7280-idp.dtsi"
11 #include "sc7280-idp-ec-h1.dtsi"
14 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)";
15 compatible = "qcom,sc7280-crd",
16 "google,hoglin-rev3", "google,hoglin-rev4",
17 "google,piglin-rev3", "google,piglin-rev4",
25 stdout-path = "serial0:115200n8";
30 regulators-2 {
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dstmmac.txt4 - compatible: Should be "snps,dwmac-<ip_version>" "snps,dwmac"
5 For backwards compatibility: "st,spear600-gmac" is also supported.
6 - reg: Address and length of the register set for the device
7 - interrupt-parent: Should be the phandle for the interrupt controller
9 - interrupts: Should contain the STMMAC interrupts
10 - interrupt-names: Should contain the interrupt names "macirq"
13 - phy-mode: See ethernet.txt file in the same directory.
14 - snps,reset-gpio gpio number for phy reset.
15 - snps,reset-active-low boolean flag to indicate if phy reset is active low.
16 - snps,reset-delays-us is triplet of delays
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-bcmcygnus/
H A Dconfigs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014-2017 Broadcom.
9 #include <asm/iproc-common/configs.h>
14 /* Post pad 3 bytes after each reg addr */
15 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
25 #define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30-engicam-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 vcc5v0_sys: vcc5v0-sys {
15 compatible = "regulator-fixed";
16 regulator-name = "vcc5v0_sys"; /* +5V */
17 regulator-always-on;
18 regulator-boot-on;
19 regulator-min-microvolt = <5000000>;
20 regulator-max-microvolt = <5000000>;
23 sdio_pwrseq: sdio-pwrseq {
24 compatible = "mmc-pwrseq-simple";
[all …]
/openbmc/linux/drivers/net/ethernet/emulex/benet/
H A Dbe_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
16 * The software must write this register twice to post any command. First,
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
39 /* Soft Reset register masks */
42 /* MPU semphore POST stage values */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
45 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-apf6.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 reg_1p8v: regulator-1p8v {
10 compatible = "regulator-fixed";
11 regulator-name = "1P8V";
12 regulator-min-microvolt = <1800000>;
13 regulator-max-microvolt = <1800000>;
14 regulator-always-on;
15 vin-supply = <&reg_3p3v>;
[all …]
H A Dimx7d-flex-concentrator.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "imx7d-tqma7.dtsi"
14 /delete-node/ &ds1339;
18 compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d";
22 /* 1024 MB - TQMa7D board configuration */
26 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
27 compatible = "regulator-fixed";
28 regulator-name = "VBUS_USBOTG2";
29 regulator-min-microvolt = <5000000>;
[all …]
H A Dmba6ulx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 model = "TQ-Systems MBA6ULx Baseboard";
18 stdout-path = &uart1;
22 compatible = "pwm-backlight";
23 power-supply = <&reg_mba6ul_3v3>;
24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
29 compatible = "gpio-beeper";
33 gpio_buttons: gpio-keys {
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-dhcor-testbench.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
17 stdout-path = "serial0:115200n8";
20 sd_switch: regulator-sd_switch {
21 compatible = "regulator-gpio";
22 regulator-name = "sd_switch";
23 regulator-min-microvolt = <1800000>;
24 regulator-max-microvolt = <2900000>;
25 regulator-type = "voltage";
26 regulator-always-on;
29 gpios-states = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5-nanopi-neo-plus2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 /dts-v1/;
6 #include "sun50i-h5.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/pinctrl/sun4i-a10.h>
14 compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
22 stdout-path = "serial0:115200n8";
26 compatible = "gpio-leds";
28 led-0 {
[all …]
H A Dsun50i-h5-nanopi-r1s-h5.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
10 /dts-v1/;
11 #include "sun50i-h5.dtsi"
12 #include "sun50i-h5-cpu-opp.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/leds/common.h>
20 compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
29 stdout-path = "serial0:115200n8";
[all …]
/openbmc/linux/drivers/mmc/core/
H A Dpwrseq_simple.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/delay.h>
39 struct gpio_descs *reset_gpios = pwrseq->reset_gpios; in mmc_pwrseq_simple_set_gpios_value()
43 int nvalues = reset_gpios->ndescs; in mmc_pwrseq_simple_set_gpios_value()
54 gpiod_set_array_value_cansleep(nvalues, reset_gpios->desc, in mmc_pwrseq_simple_set_gpios_value()
55 reset_gpios->info, values); in mmc_pwrseq_simple_set_gpios_value()
63 struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq); in mmc_pwrseq_simple_pre_power_on()
65 if (!IS_ERR(pwrseq->ext_clk) && !pwrseq->clk_enabled) { in mmc_pwrseq_simple_pre_power_on()
66 clk_prepare_enable(pwrseq->ext_clk); in mmc_pwrseq_simple_pre_power_on()
67 pwrseq->clk_enabled = true; in mmc_pwrseq_simple_pre_power_on()
[all …]
/openbmc/linux/arch/arm/boot/dts/actions/
H A Dowl-s500-roseapplepi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (C) 2020-2021 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
8 /dts-v1/;
10 #include "owl-s500.dtsi"
22 stdout-path = "serial2:115200n8";
30 syspwr: regulator-5v0 {
31 compatible = "regulator-fixed";
32 regulator-name = "SYSPWR";
33 regulator-min-microvolt = <5000000>;
34 regulator-max-microvolt = <5000000>;
[all …]
/openbmc/linux/drivers/w1/
H A Dw1_io.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/delay.h>
48 * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level.
50 * @bit: 0 - write a 0, 1 - write a 0 read the level
54 if (dev->bus_master->touch_bit) in w1_touch_bit()
55 return dev->bus_master->touch_bit(dev->bus_master->data, bit); in w1_touch_bit()
66 * w1_write_bit() - Generates a write-0 or write-1 cycle.
70 * Only call if dev->bus_master->touch_bit is NULL
79 dev->bus_master->write_bit(dev->bus_master->data, 0); in w1_write_bit()
81 dev->bus_master->write_bit(dev->bus_master->data, 1); in w1_write_bit()
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j7200-evm-quad-port-eth-exp.dtso1 // SPDX-License-Identifier: GPL-2.0
3 * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
6 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
14 #include "k3-pinctrl.h"
15 #include "k3-serdes.h"
19 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
20 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
21 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
[all …]
H A Dk3-j721e-evm-quad-port-eth-exp.dtso1 // SPDX-License-Identifier: GPL-2.0
3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
6 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/phy/phy-cadence.h>
16 #include "k3-pinctrl.h"
17 #include "k3-serdes.h"
21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
40 /* PLL stabilization delay in usec */
55 * @param divp post divider 2^n
59 * @returns monotonic time in us that the PLL will be stable
71 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77 * Read low-level parameters of a PLL.
82 * @param divp returns post divider 2^n
86 * @returns 0 if ok, -1 on error (invalid clock id)
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dsram243x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram243x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
69 /* reset entry mode for dllctrl */
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
[all …]
H A Dsram242x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram242x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
69 /* reset entry mode for dllctrl */
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-s3-pinecube.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
6 /dts-v1/;
7 #include "sun8i-v3.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
38 compatible = "regulator-fixed";
39 regulator-name = "vcc5v0";
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun50i-h5-nanopi-neo-plus2.dts5 * This file is dual-licensed: you can use it either under the terms
44 /dts-v1/;
45 #include "sun50i-h5.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
48 #include <dt-bindings/input/input.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
61 stdout-path = "serial0:115200n8";
65 compatible = "gpio-leds";
70 default-state = "on";
[all …]

1234567891011