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/openbmc/qemu/hw/audio/
H A Dpl041.hx12 /* PL041 register file description */
14 REGISTER( rxcr1, 0x00 )
15 REGISTER( txcr1, 0x04 )
16 REGISTER( sr1, 0x08 )
17 REGISTER( isr1, 0x0C )
18 REGISTER( ie1, 0x10 )
19 REGISTER( rxcr2, 0x14 )
20 REGISTER( txcr2, 0x18 )
21 REGISTER( sr2, 0x1C )
22 REGISTER( isr2, 0x20 )
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dimmap_5445x.h75 u16 sbfsr; /* Serial Boot Facility Status Register */
77 u16 sbfcr; /* Serial Boot Facility Control Register */
89 u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
92 u16 cir; /* Chip Identification Register (Read-only) */
94 u16 misccr; /* Miscellaneous Control Register */
95 u16 cdr; /* Clock Divider Register */
96 u16 uocsr; /* USB On-the-Go Controller Status Register */
101 u8 podr_fec0h; /* FEC0 High Port Output Data Register */
102 u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
103 u8 podr_ssi; /* SSI Port Output Data Register */
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_86xx.h21 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
23 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
25 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
27 uint bptr; /* 0x20 - Boot Page Translation Register */
29 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
31 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
33 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
35 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
37 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
39 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
[all …]
H A Dprocessor.h13 /* Machine State Register (MSR) Fields */
60 /* Floating Point Status and Control Register (FPSCR) Fields */
92 #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
94 #define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
96 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
97 #define SPRN_CTR 0x009 /* Count Register */
98 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
106 #define SPRN_DAR 0x013 /* Data Address Register */
107 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
108 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
[all …]
H A Dfsl_pci.h33 * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
69 u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */
70 u32 cfg_data; /* 0x004 - PCI Configuration Data Register */
71 u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */
72 u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */
73 u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */
74 u32 config; /* 0x014 - PCIE CONFIG Register */
75 u32 int_status; /* 0x018 - PCIE interrupt status register */
77 u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */
78 u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
[all …]
H A Dimmap_83xx.h27 u32 bar; /* LBIU local access window base address register */
28 u32 ar; /* LBIU local access window attribute register */
35 u32 immrbar; /* Internal memory map base address register */
37 u32 altcbar; /* Alternate configuration base address register */
47 u32 sgprl; /* System General Purpose Register Low */
48 u32 sgprh; /* System General Purpose Register High */
49 u32 spridr; /* System Part and Revision ID Register */
51 u32 spcr; /* System Priority Configuration Register */
52 u32 sicrl; /* System I/O Configuration Register Low */
53 u32 sicrh; /* System I/O Configuration Register High */
[all …]
/openbmc/u-boot/include/linux/
H A Dimmap_qe.h40 u32 iadd; /* I-RAM Address Register */
41 u32 idata; /* I-RAM Data Register */
72 u32 cecr; /* QE command register */
73 u32 ceccr; /* QE controller configuration register */
74 u32 cecdr; /* QE command data register */
76 u16 ceter; /* QE timer event register */
78 u16 cetmr; /* QE timers mask register */
79 u32 cetscr; /* QE time-stamp timer control register */
80 u32 cetsr1; /* QE time-stamp register 1 */
81 u32 cetsr2; /* QE time-stamp register 2 */
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_mc_static.h11 {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
13 {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
15 {0x00001404, 0x3630b800}, /*Dunit Control Low Register */
16 {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
17 /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
18 {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
21 {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
23 {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
26 {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
27 {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_pio.h39 u32 per; /* 0x00 PIO Enable Register */
40 u32 pdr; /* 0x04 PIO Disable Register */
41 u32 psr; /* 0x08 PIO Status Register */
43 u32 oer; /* 0x10 Output Enable Register */
45 u32 osr; /* 0x18 Output Status Register */
47 u32 ifer; /* 0x20 Input Filter Enable Register */
48 u32 ifdr; /* 0x24 Input Filter Disable Register */
49 u32 ifsr; /* 0x28 Input Filter Status Register */
51 u32 sodr; /* 0x30 Set Output Data Register */
52 u32 codr; /* 0x34 Clear Output Data Register */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_arria10_socdk_sdmmc_handoff.dtsi128 nocclk = <0x0384000b>; /* Register: nocclk */
129 mpuclk = <0x03840001>; /* Register: mpuclk */
150 pinctrl-single,register-width = <32>;
153 <0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */
154 <0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */
155 <0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */
156 <0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */
157 <0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */
158 <0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */
159 <0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dclk.h17 u32 boot_map; /* Boot Map Control Register */
19 u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */
21 u32 start_er_int; /* Start Enable Register */
22 u32 start_rsr_int; /* Start Raw Status Register */
23 u32 start_sr_int; /* Start Status Register */
24 u32 start_apr_int; /* Start Activation Polarity Register */
26 u32 start_er_pin; /* Start Enable Register */
27 u32 start_rsr_pin; /* Start Raw Status Register */
28 u32 start_sr_pin; /* Start Status Register */
29 u32 start_apr_pin; /* Start Activation Polarity Register */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun9i.h3 * Sun8i platform dram controller register and constant defines
16 u32 ccr; /* 0x04 controller configuration register */
41 u32 mstr; /* 0x00 master register */
42 u32 stat; /* 0x04 operating mode status register */
44 u32 mrctrl[2]; /* 0x10 mode register read/write control reg */
45 u32 mstat; /* 0x18 mode register read/write status reg */
47 u32 derateen; /* 0x20 temperature derate enable register */
48 u32 derateint; /* 0x24 temperature derate interval register */
50 u32 pwrctl; /* 0x30 low power control register */
51 u32 pwrtmg; /* 0x34 low power timing register */
[all …]
H A Ddram_sun4i.h8 * Sunxi platform dram register definition.
15 u32 ccr; /* 0x00 controller configuration register */
16 u32 dcr; /* 0x04 dram configuration register */
17 u32 iocr; /* 0x08 i/o configuration register */
18 u32 csr; /* 0x0c controller status register */
19 u32 drr; /* 0x10 dram refresh register */
20 u32 tpr0; /* 0x14 dram timing parameters register 0 */
21 u32 tpr1; /* 0x18 dram timing parameters register 1 */
22 u32 tpr2; /* 0x1c dram timing parameters register 2 */
23 u32 gdllcr; /* 0x20 global dll control register */
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/hplip/hplip/
H A D0001-Drop-using-register-storage-classifier.patch4 Subject: [PATCH] Drop using register storage classifier
30 -void dct_forward (register int *block_p)
35 @@ -257,7 +257,7 @@ void dct_forward (register int *block_p)
39 -void dct_inverse (register int *block_p)
52 -void dct_forward (register int *block_p);
55 -void dct_inverse (register int *block_p);
67 - register char *dptr=dest;
80 - register BYTE *outptr = outmem;
81 - register uint32_t col;
95 - * address, which can be held in a register in the inner loops on many
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmc_me_regs.h112 /* DEC200 Peripheral Control Register */
114 /* 2D-ACE Peripheral Control Register */
116 /* ENET Peripheral Control Register */
118 /* DMACHMUX0 Peripheral Control Register */
120 /* CSI0 Peripheral Control Register */
122 /* MMDC0 Peripheral Control Register */
124 /* FRAY Peripheral Control Register */
126 /* PIT0 Peripheral Control Register */
128 /* FlexTIMER0 Peripheral Control Register */
130 /* SARADC0 Peripheral Control Register */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dscg.h30 /* SCG DDR Clock Control Register */
37 /* SCG NIC Clock Control Register */
56 /* SCG NIC clock status register */
71 /* SCG Slow IRC Control Status Register */
78 /* SCG Slow IRC Configuration Register */
84 /* SCG Slow IRC Divide Register */
99 /* SCG Fast IRC Control Status Register */
106 /* SCG Fast IRC Divide Register */
122 /* SCG System OSC Control Status Register */
126 /* SCG Fast IRC Divide Register */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h96 #define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */
97 #define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */
98 #define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */
99 #define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */
100 #define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */
101 #define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */
102 #define DCSR6 0x40000018 /* DMA Control / Status Register for Channel 6 */
103 #define DCSR7 0x4000001c /* DMA Control / Status Register for Channel 7 */
104 #define DCSR8 0x40000020 /* DMA Control / Status Register for Channel 8 */
105 #define DCSR9 0x40000024 /* DMA Control / Status Register for Channel 9 */
[all …]
/openbmc/u-boot/board/freescale/c29xpcie/
H A Dcpld.h12 * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
15 u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */
16 u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */
17 u8 hwver; /* 0x2 - Hardware Version Register */
18 u8 cpldver; /* 0x3 - Software Version Register */
20 u8 rstcon; /* 0x10 - Reset control register */
21 u8 flhcsr; /* 0x11 - Flash control and status Register */
22 u8 wdcsr; /* 0x12 - Watchdog control and status Register */
23 u8 wdkick; /* 0x13 - Watchdog kick Register */
24 u8 fancsr; /* 0x14 - Fan control and status Register */
[all …]
/openbmc/qemu/include/hw/sd/
H A Dsdhci.h54 uint32_t sdmasysad; /* SDMA System Address register */
57 uint32_t argument; /* Command Argument Register */
58 uint16_t trnmod; /* Transfer Mode Setting Register */
59 uint16_t cmdreg; /* Command Register */
61 uint32_t prnsts; /* Present State Register */
62 uint8_t hostctl1; /* Host Control Register */
63 uint8_t pwrcon; /* Power control Register */
64 uint8_t blkgap; /* Block Gap Control Register */
65 uint8_t wakcon; /* WakeUp Control Register */
66 uint16_t clkcon; /* Clock control Register */
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Datmel_nand_ecc.h10 #define ATMEL_ECC_CR 0x00 /* Control register */
13 #define ATMEL_ECC_MR 0x04 /* Mode register */
20 #define ATMEL_ECC_SR 0x08 /* Status register */
25 #define ATMEL_ECC_PR 0x0c /* Parity register */
29 #define ATMEL_ECC_NPR 0x10 /* NParity register */
32 /* Register access macros for PMECC */
42 /* PMECC Register Definitions */
45 u32 cfg; /* 0x00 PMECC Configuration Register */
46 u32 sarea; /* 0x04 PMECC Spare Area Size Register */
47 u32 saddr; /* 0x08 PMECC Start Address Register */
[all …]
/openbmc/u-boot/drivers/ata/
H A Ddwc_ahsata_priv.h19 /* Generic Host Register */
21 /* HBA Capabilities Register */
44 /* Global HBA Control Register */
49 /* Interrupt Status Register */
51 /* Ports Implemented Register */
53 /* AHCI Version Register */
69 /* HBA Capabilities Extended Register */
72 /* BIST Activate FIS Register */
78 /* BIST Control Register */
91 /* BIST FIS Count Register */
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-quark/
H A Dmsg_port.h13 * register (MCR), Message Control Register eXtension (MCRX) and the
14 * message data register (MDR).
16 #define MSG_CTRL_REG 0xd0 /* Message Control Register */
17 #define MSG_DATA_REG 0xd4 /* Message Data Register */
18 #define MSG_CTRL_EXT_REG 0xd8 /* Message Control Register EXT */
38 * msg_port_setup - set up the message port control register
42 * @reg: register number within a port
47 * msg_port_read - read a message port register using normal opcode
50 * @reg: register number within a port
52 * @return: message port register value
[all …]
/openbmc/u-boot/board/gdsys/common/
H A Dch7301.c17 CH7301_CM = 0x1c, /* Clock Mode Register */
18 CH7301_IC = 0x1d, /* Input Clock Register */
19 CH7301_GPIO = 0x1e, /* GPIO Control Register */
20 CH7301_IDF = 0x1f, /* Input Data Format Register */
21 CH7301_CD = 0x20, /* Connection Detect Register */
22 CH7301_DC = 0x21, /* DAC Control Register */
23 CH7301_HPD = 0x23, /* Hot Plug Detection Register */
24 CH7301_TCTL = 0x31, /* DVI Control Input Register */
25 CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
26 CH7301_TPD = 0x34, /* DVI PLL Divide Register */
[all …]
/openbmc/qemu/hw/intc/
H A Dimx_avic.c119 case 1: /* Normal Interrupt Mask Register, NIMASK */ in imx_avic_read()
122 case 2: /* Interrupt Enable Number Register, INTENNUM */ in imx_avic_read()
123 case 3: /* Interrupt Disable Number Register, INTDISNUM */ in imx_avic_read()
126 case 4: /* Interrupt Enabled Number Register High */ in imx_avic_read()
129 case 5: /* Interrupt Enabled Number Register Low */ in imx_avic_read()
132 case 6: /* Interrupt Type Register High */ in imx_avic_read()
135 case 7: /* Interrupt Type Register Low */ in imx_avic_read()
138 case 8: /* Normal Interrupt Priority Register 7 */ in imx_avic_read()
139 case 9: /* Normal Interrupt Priority Register 6 */ in imx_avic_read()
140 case 10:/* Normal Interrupt Priority Register 5 */ in imx_avic_read()
[all …]
/openbmc/u-boot/include/
H A Dfsl_sec.h45 u32 rtmctl; /* misc. control register */
46 u32 rtscmisc; /* statistical check misc. register */
47 u32 rtpkrrng; /* poker range register */
51 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
52 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
56 u32 rtsdctl; /* seed control register */
58 u32 rtsblim; /* PRGM=1: sparse bit limit register */
59 u32 rttotsam; /* PRGM=0: total samples register */
61 u32 rtfreqmin; /* frequency count min. limit register */
64 u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
[all …]

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