1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2a8d9758dSMingkai Hu /** 3a8d9758dSMingkai Hu * Copyright 2013 Freescale Semiconductor 4a8d9758dSMingkai Hu * Author: Mingkai Hu <Mingkai.Hu@freescale.com> 5a8d9758dSMingkai Hu * Po Liu <Po.Liu@freescale.com> 6a8d9758dSMingkai Hu * 7a8d9758dSMingkai Hu * This file provides support for the ngPIXIS, a board-specific FPGA used on 8a8d9758dSMingkai Hu * some Freescale reference boards. 9a8d9758dSMingkai Hu */ 10a8d9758dSMingkai Hu 11a8d9758dSMingkai Hu /* 12a8d9758dSMingkai Hu * CPLD register set. Feel free to add board-specific #ifdefs where necessary. 13a8d9758dSMingkai Hu */ 14a8d9758dSMingkai Hu struct cpld_data { 15a8d9758dSMingkai Hu u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */ 16a8d9758dSMingkai Hu u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */ 17a8d9758dSMingkai Hu u8 hwver; /* 0x2 - Hardware Version Register */ 18a8d9758dSMingkai Hu u8 cpldver; /* 0x3 - Software Version Register */ 19a8d9758dSMingkai Hu u8 res[12]; 20a8d9758dSMingkai Hu u8 rstcon; /* 0x10 - Reset control register */ 21a8d9758dSMingkai Hu u8 flhcsr; /* 0x11 - Flash control and status Register */ 22a8d9758dSMingkai Hu u8 wdcsr; /* 0x12 - Watchdog control and status Register */ 23a8d9758dSMingkai Hu u8 wdkick; /* 0x13 - Watchdog kick Register */ 24a8d9758dSMingkai Hu u8 fancsr; /* 0x14 - Fan control and status Register */ 25a8d9758dSMingkai Hu u8 ledcsr; /* 0x15 - LED control and status Register */ 26a8d9758dSMingkai Hu u8 misccsr; /* 0x16 - Misc control and status Register */ 27a8d9758dSMingkai Hu u8 bootor; /* 0x17 - Boot configure override Register */ 28a8d9758dSMingkai Hu u8 bootcfg1; /* 0x18 - Boot configure 1 Register */ 29a8d9758dSMingkai Hu u8 bootcfg2; /* 0x19 - Boot configure 2 Register */ 30a8d9758dSMingkai Hu u8 bootcfg3; /* 0x1a - Boot configure 3 Register */ 31a8d9758dSMingkai Hu u8 bootcfg4; /* 0x1b - Boot configure 4 Register */ 32a8d9758dSMingkai Hu }; 33a8d9758dSMingkai Hu 34a8d9758dSMingkai Hu #define CPLD_BANKSEL_EN 0x02 35a8d9758dSMingkai Hu #define CPLD_BANKSEL_MASK 0x3f 36a8d9758dSMingkai Hu #define CPLD_SELECT_BANK1 0xc0 37a8d9758dSMingkai Hu #define CPLD_SELECT_BANK2 0x80 38a8d9758dSMingkai Hu #define CPLD_SELECT_BANK3 0x40 39a8d9758dSMingkai Hu #define CPLD_SELECT_BANK4 0x00 40