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/openbmc/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,dra7-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,dra7-dss"
12 - reg: address and length of the register spaces for 'dss'
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
16 - syscon: phandle to control module core syscon node
23 - reg: address and length of the register spaces for 'pll1_clkctrl',
25 - clocks: handle to video1 pll clock and video2 pll clock
[all …]
H A Dti,omap5-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
[all …]
H A Dti,omap4-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap4-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, VENC, DSI, HDMI
22 - Video port for DPI output
[all …]
H A Dti,omap3-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap3-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - Video ports:
19 - Port 0: DPI output
20 - Port 1: SDI output
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/openbmc/linux/Documentation/arch/x86/x86_64/
H A Dfsgs.rst1 .. SPDX-License-Identifier: GPL-2.0
10 Segment-register:Byte-address
12 The segment base address is added to the Byte-address to compute the
14 instances of data with the identical Byte-address, i.e. the same code. The
15 selection of a particular instance is purely based on the base-address in
18 In 32-bit mode the CPU provides 6 segments, which also support segment
21 In 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is
23 still functional in 64-bit mode.
26 ------------------------------
42 ------------------------------------------
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/openbmc/linux/arch/mips/include/asm/sgi/
H A Dip22.h17 * 'spaces', the 'space' determines where and how to enable/disable
21 * HAL2 driver). This will prevent many complications, trust me ;-)
33 #define SGINT_END (SGINT_CPU+40) /* End of 'spaces' */
49 #define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */
55 #define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */
65 #define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */
75 #define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
77 extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
78 extern unsigned short ip22_nvram_read(int reg);
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
19 Configuration Spaces.
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
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/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dti_hecc.txt8 - compatible: "ti,am3517-hecc"
9 - reg: addresses and lengths of the register spaces for 'hecc', 'hecc-ram'
11 - reg-names :"hecc", "hecc-ram", "mbx"
12 - interrupts: interrupt mapping for the hecc interrupts sources
13 - clocks: clock phandles (see clock bindings for details)
16 - ti,use-hecc1int: if provided configures HECC to produce all interrupts
19 - xceiver-supply: regulator that powers the CAN transceiver
25 compatible = "ti,am3517-hecc";
26 reg = <0x5c050000 0x80>,
29 reg-names = "hecc", "hecc-ram", "mbx";
/openbmc/u-boot/doc/device-tree-bindings/video/osd/
H A Dgdsys,ihs_video_out.txt4 - compatible: "gdsys,ihs_video_out"
5 - reg: A combination of three register spaces:
6 - Register base for the video registers
7 - Register base for the OSD registers
8 - Address of the OSD video memory
9 - mode: The initial resolution and frequency: "1024_768_60", "720_400_70", or
11 - clk_gen: phandle to the pixel clock generator
12 - dp_tx: phandle to the display associated with the OSD
18 reg = <0x100 0x40
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmarvell,pxa168.txt8 - compatible: should be one of the following.
9 - "marvell,pxa168-clock" - controller compatible with PXA168 SoC.
11 - reg: physical base address of the clock subsystem and length of memory mapped
13 "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
15 - #clock-cells: should be 1.
16 - #reset-cells: should be 1.
21 All these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>.
H A Dmarvell,pxa910.txt8 - compatible: should be one of the following.
9 - "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
11 - reg: physical base address of the clock subsystem and length of memory mapped
13 "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
15 - #clock-cells: should be 1.
16 - #reset-cells: should be 1.
21 All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dda8xx-usb.txt3 For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms.
7 - compatible : Should be set to "ti,da830-musb".
9 - reg: Offset and length of the USB controller register set.
11 - interrupts: The USB interrupt number.
13 - interrupt-names: Should be set to "mc".
15 - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg".
17 - phys: Phandle for the PHY device
19 - phy-names: Should be "usb-phy"
21 - dmas: specifies the dma channels
23 - dma-names: specifies the names of the channels. Use "rxN" for receive
[all …]
H A Dam33xx-usb.txt3 - compatible: ti,am33xx-usb
4 - reg: offset and length of the usbss register sets
5 - ti,hwmods : must be "usb_otg_hs"
13 - compatible: ti,am335x-usb-ctrl-module
14 - reg: offset and length of the "USB control registers" in the "Control
17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
22 compatible: ti,am335x-usb-phy
23 reg: offset and length of the "USB PHY" register space
25 reg-names: phy
31 - compatible: ti,musb-am33xx
[all …]
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dinterlaken-lac.txt2 Freescale Interlaken Look-Aside Controller Device Bindings
6 - Interlaken Look-Aside Controller (LAC) Node
7 - Example LAC Node
8 - Interlaken Look-Aside Controller (LAC) Software Portal Node
9 - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
10 - Example LAC SWP Node with Child Nodes
13 Interlaken Look-Aside Controller (LAC) Node
17 The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
18 facilitate interoperability between a data path device and a look-aside
19 co-processor, the Interlaken Look-Aside protocol is defined for short
[all …]
/openbmc/linux/arch/mips/include/asm/sn/sn0/
H A Daddrs.h8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
19 * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
25 * should this change, the base registers may very well become processor-
28 * For more information on the address spaces, see the "Local Resources"
32 * files. Please bracket any language-dependent definitions
45 * whether the system is running in N-mode (more nodes with less memory)
46 * or M-mode (fewer nodes with more memory). We expect that it will
65 #else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */
105 #define BWIN_SIZEMASK (BWIN_SIZE - 1)
129 * The following define the major position-independent aliases used
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/openbmc/qemu/target/avr/
H A Dcpu.h4 * Copyright (c) 2016-2020 Michael Rolnik
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
24 #include "cpu-qom.h"
25 #include "exec/cpu-defs.h"
28 #error "AVR 8-bit does not support user mode"
34 * AVR has two memory spaces, data & code.
54 * spaces that both have start from zero but have to go somewhere in
83 AVR_FEATURE_RMW, /* Read Modify Write - XCH LAC LAS LAT */
170 int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
171 int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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/openbmc/linux/arch/alpha/include/asm/
H A Dcore_irongate.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
10 * which provides memory controller and PCI access for NAUTILUS-based
21 * The 21264 supports, and internally recognizes, a 44-bit physical
30 * through the routines given is 32-bit.
38 igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */
39 igcsr32 stat_cmd; /* 0x04 - status, command */
40 igcsr32 class; /* 0x08 - class code, rev ID */
41 igcsr32 latency; /* 0x0C - header type, PCI latency */
42 igcsr32 bar0; /* 0x10 - BAR0 - AGP */
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/openbmc/qemu/include/hw/i386/
H A Dintel_iommu.h2 * QEMU emulation of an Intel IOMMU (VT-d)
25 #include "hw/i386/x86-iommu.h"
26 #include "qemu/iova-tree.h"
29 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
32 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
49 #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
66 /* Context-Entry */
136 * registered drivers (e.g. vfio-pci) on either:
139 * VFIO_IOMMU_MAP_DMA, -EEXIST will trigger), or,
143 * That accuracy is not required for UNMAP-only notifiers, but it is a
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/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dcgs_common.h32 * enum cgs_ind_reg - Indirect register spaces
45 * enum cgs_ucode_id - Firmware types for different IPs
65 * struct cgs_firmware_info - Firmware information
84 * cgs_read_register() - Read an MMIO register
93 * cgs_write_register() - Write an MMIO register
102 * cgs_read_ind_register() - Read an indirect register
112 * cgs_write_ind_register() - Write an indirect register
120 #define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT argument
121 #define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK argument
123 #define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \ argument
[all …]
/openbmc/u-boot/board/imgtec/malta/
H A Dmalta.c1 // SPDX-License-Identifier: GPL-2.0
38 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); in malta_lcd_puts() local
42 __raw_writel(str[i], reg); in malta_lcd_puts()
43 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; in malta_lcd_puts()
46 /* fill the rest of the display with spaces */ in malta_lcd_puts()
48 __raw_writel(' ', reg); in malta_lcd_puts()
49 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; in malta_lcd_puts()
56 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION); in malta_core_card() local
58 rev = __raw_readl(reg); in malta_core_card()
89 gd->ram_size = CONFIG_SYS_MEM_SIZE; in dram_init()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dnvidia,tegra186-gpio.txt42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
52 both the overall controller HW module and the sets-of-ports as "controllers".
56 interrupt signals generated by a set-of-ports. The intent is for each generated
59 per-port-set signals is reported via a separate register. Thus, a driver needs
66 - compatible
69 - "nvidia,tegra186-gpio".
70 - "nvidia,tegra186-gpio-aon".
71 - reg-names
73 Contains a list of names for the register spaces described by the reg
[all …]
/openbmc/linux/arch/arc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
88 source "arch/arc/plat-tb10x/Kconfig"
89 source "arch/arc/plat-axs10x/Kconfig"
90 source "arch/arc/plat-hsdk/Kconfig"
108 ISA for the Next Generation ARC-HS cores
126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
127 Shared Address Spaces (for sharing TLB entries in MMU)
128 -Caches: New Prog Model, Region Flush
129 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
[all …]
/openbmc/linux/Documentation/devicetree/bindings/fsi/
H A Dfsi.txt4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
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