1ab08aefcSChao Xie* Marvell PXA168 Clock Controller 2ab08aefcSChao Xie 3ab08aefcSChao XieThe PXA168 clock subsystem generates and supplies clock to various 4ab08aefcSChao Xiecontrollers within the PXA168 SoC. 5ab08aefcSChao Xie 6ab08aefcSChao XieRequired Properties: 7ab08aefcSChao Xie 8ab08aefcSChao Xie- compatible: should be one of the following. 9ab08aefcSChao Xie - "marvell,pxa168-clock" - controller compatible with PXA168 SoC. 10ab08aefcSChao Xie 11ab08aefcSChao Xie- reg: physical base address of the clock subsystem and length of memory mapped 12ab08aefcSChao Xie region. There are 3 places in SOC has clock control logic: 13ab08aefcSChao Xie "mpmu", "apmu", "apbc". So three reg spaces need to be defined. 14ab08aefcSChao Xie 15ab08aefcSChao Xie- #clock-cells: should be 1. 16ab08aefcSChao Xie- #reset-cells: should be 1. 17ab08aefcSChao Xie 18ab08aefcSChao XieEach clock is assigned an identifier and client nodes use this identifier 19ab08aefcSChao Xieto specify the clock which they consume. 20ab08aefcSChao Xie 21ab08aefcSChao XieAll these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>. 22