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/openbmc/linux/drivers/phy/ti/
H A Dphy-j721e-wiz.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
13 #include <linux/clk-provider.h>
19 #include <linux/mux/consumer.h>
25 #include <linux/reset-controller.h>
44 /* To include mux clocks, divider clocks and gate clocks */
125 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
126 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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H A Damlogic,gxl-mdio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/amlogic,gxl-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jerome Brunet <jbrunet@baylibre.com>
18 - $ref: mdio-mux.yaml#
22 const: amlogic,gxl-mdio-mux
30 clock-names:
32 - const: ref
35 - compatible
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H A Dti,k3-am654-cpts.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
17 - selection of multiple external clock sources
18 - Software control of time sync events via interrupt or polling
19 - 64-bit timestamp mode in ns with PPM and nudge adjustment.
20 - hardware timestamp push inputs (HWx_TS_PUSH)
[all …]
H A Drenesas,etheravb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt7620-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt7620-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
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H A Dmediatek,mt7621-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt7621-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
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H A Dmediatek,mt76x8-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt76x8-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt76x8-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
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/openbmc/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-wpcm450.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
27 compatible = "arm,arm926ej-s";
33 clk24m: clock-24mhz {
35 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
[all …]
/openbmc/linux/drivers/net/ethernet/ti/
H A Dcpts.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
32 #define cpts_read32(c, r) readl_relaxed(&c->reg->r)
33 #define cpts_write32(c, v, r) writel_relaxed(v, &c->reg->r)
37 return (event->high >> PORT_NUMBER_SHIFT) & PORT_NUMBER_MASK; in cpts_event_port()
42 return time_after(jiffies, event->tmo); in event_expired()
47 return (event->high >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; in event_type()
60 return -1; in cpts_fifo_pop()
69 list_for_each_safe(this, next, &cpts->events) { in cpts_purge_events()
72 list_del_init(&event->list); in cpts_purge_events()
[all …]
H A Dam65-cpts.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
9 #include <linux/clk-provider.h>
23 #include "am65-cpts.h"
164 struct clk *refclk; member
201 #define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
202 #define am65_cpts_read32(c, r) readl(&(c)->reg->r)
219 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7; in am65_cpts_set_add_val()
221 am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val); in am65_cpts_set_add_val()
232 return (event->event1 & AM65_CPTS_EVENT_1_PORT_NUMBER_MASK) >> in am65_cpts_event_get_port()
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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H A Dti,phy-am654-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Kishon Vijay Abraham I <kishon@ti.com>
19 - ti,phy-am654-serdes
24 reg-names:
26 - const: serdes
28 power-domains:
34 Three input clocks referring to left input reference clock, refclk and right input reference
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/openbmc/u-boot/arch/arm/dts/
H A Darmada-385-atl-x530.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/gpio/gpio.h>
4 #include "armada-385.dtsi"
11 stdout-path = "serial0:115200n8";
30 pcie-mem-aperture = <0xa0000000 0x40000000>;
33 eco-button-interrupt {
34 compatible = "atl,eco-button-interrupt";
35 eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
38 board-reset {
40 /* Physical board layout of reset pin is active-low but for the
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
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H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
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/openbmc/linux/sound/soc/codecs/
H A Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
18 #include <linux/irqchip/irq-madera.h>
22 #include <sound/madera-pdata.h>
24 #include <dt-bindings/sound/madera.h>
143 dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
145 dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
147 dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
150 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
152 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
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/openbmc/qemu/include/hw/misc/
H A Dstm32l4x5_rcc_internals.h4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
24 #define TYPE_RCC_CLOCK_MUX "stm32l4x5-rcc-clock-mux"
25 #define TYPE_RCC_PLL "stm32l4x5-rcc-pll"
401 pll->id = id; in set_pll_init_info()
402 pll->vco_multiplier = 1; in set_pll_init_info()
404 pll->channel_enabled[i] = false; in set_pll_init_info()
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2e-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
H A Dkeystone-k2l-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
H A Dkeystone-k2hk-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x4000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Ddra7xx_iodelay.c1 // SPDX-License-Identifier: GPL-2.0+
21 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ, in isolate_io()
23 clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ, in isolate_io()
28 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, in isolate_io()
31 (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) in isolate_io()
35 clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, in isolate_io()
38 readl((*ctrl)->ctrl_core_sma_sw_0); in isolate_io()
41 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, in isolate_io()
45 (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) in isolate_io()
55 /* Configure REFCLK period */ in calibrate_iodelay()
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
147 * @refclk: Our reference clock.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
159 * serves double-duty of keeping track of the direction and
165 * each other's read-modify-write.
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-h100.dts4 * This file is dual-licensed: you can use it either under the terms
42 /dts-v1/;
45 #include "imx6qdl-sr-som.dtsi"
46 #include "imx6qdl-sr-som-brcm.dtsi"
64 stdout-path = &uart2;
67 hdmi_osc: hdmi-osc {
68 compatible = "fixed-clock";
69 clock-output-names = "hdmi-osc";
70 clock-frequency = <27000000>;
71 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/mips/cavium-octeon/
H A Docteon-platform.c6 * Copyright (C) 2004-2017 Cavium, Inc.
18 #include <asm/octeon/cvmx-helper-board.h>
24 #include <asm/octeon/cvmx-uctlx-defs.h>
78 if (dev->of_node) { in octeon2_usb_clocks_start()
82 uctl_node = of_get_parent(dev->of_node); in octeon2_usb_clocks_start()
88 "refclk-frequency", &clock_rate); in octeon2_usb_clocks_start()
90 dev_err(dev, "No UCTL \"refclk-frequency\"\n"); in octeon2_usb_clocks_start()
95 "refclk-type", &clock_type); in octeon2_usb_clocks_start()
203 * Step 4: Program the power-on reset field in the UCTL in octeon2_usb_clocks_start()
204 * clock-reset-control register. in octeon2_usb_clocks_start()
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