Lines Matching +full:refclk +full:- +full:mux
4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
24 #define TYPE_RCC_CLOCK_MUX "stm32l4x5-rcc-clock-mux"
25 #define TYPE_RCC_PLL "stm32l4x5-rcc-pll"
401 pll->id = id; in set_pll_init_info()
402 pll->vco_multiplier = 1; in set_pll_init_info()
404 pll->channel_enabled[i] = false; in set_pll_init_info()
405 pll->channel_exists[i] = PLL_INIT_INFO[id].channel_exists[i]; in set_pll_init_info()
406 pll->channel_divider[i] = PLL_INIT_INFO[id].default_channel_divider[i]; in set_pll_init_info()
410 /* Clock mux init info */
450 .name = "pll-input",
485 .name = "hse-divided-by-32",
495 .name = "lcd-and-rtc-common-mux",
508 .name = "cortex-refclk",
510 /* REFCLK is always HCLK/8 */
1020 .name = "cortex-fclk",
1028 static inline void set_clock_mux_init_info(RccClockMuxState *mux, in set_clock_mux_init_info() argument
1031 mux->id = id; in set_clock_mux_init_info()
1032 mux->multiplier = CLOCK_MUX_INIT_INFO[id].multiplier; in set_clock_mux_init_info()
1033 mux->divider = CLOCK_MUX_INIT_INFO[id].divider; in set_clock_mux_init_info()
1034 mux->enabled = CLOCK_MUX_INIT_INFO[id].enabled; in set_clock_mux_init_info()
1039 mux->src = 0; in set_clock_mux_init_info()