/openbmc/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_read_leveling.c | 1 // SPDX-License-Identifier: GPL-2.0 55 * Desc: Execute the Read leveling phase by HW 56 * Args: dram_info - main struct 57 * freq - current sequence frequency 65 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw() 66 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw() 68 /* Start Auto Read Leveling procedure */ in ddr3_read_leveling_hw() 74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw() 76 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw() 91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local [all …]
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H A D | ddr3_axp_training_static.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 10 * STATIC_TRAINING - Set only if static parameters for training are set and 15 /* Read Leveling */ 56 /*center DQS on read cycle */ 59 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 60 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 68 /* Read Leveling */ 129 /*center DQS on read cycle */ 132 {0x00001538, 0x0000000D}, /*Read Data Sample Delays Register */ 133 {0x0000153C, 0x00000011}, /*Read Data Ready Delay Register */ [all …]
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/openbmc/u-boot/board/gateworks/gw_ventana/ |
H A D | gw_ventana_spl.c | 1 // SPDX-License-Identifier: GPL-2.0+ 10 #include <asm/arch/mx6-ddr.h> 11 #include <asm/arch/mx6-pins.h> 13 #include <asm/mach-imx/boot_mode.h> 14 #include <asm/mach-imx/iomux-v3.h> 15 #include <asm/mach-imx/mxc_i2c.h> 35 /* SDCKE[0:1]: 100k pull-up */ 38 /* SDBA2: pull-up disabled */ 40 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 95 /* SDCKE[0:1]: 100k pull-up */ [all …]
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/openbmc/linux/include/soc/at91/ |
H A D | at91sam9_ddrsdr.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */ 48 #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Onl… 51 #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ 52 #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ 53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ 54 #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ 55 #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ 57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ 58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from 8 - reg: Must contains offset/length value for controller. 10 - #address-cells: Must be 2. The partition number has to be encoded in the 11 first address cell and it may accept values 0..N-1 12 (N - total number of partitions). The second cell is the 15 - #size-cells: Must be set to 1. 17 - ranges: Must contain one or more chip select memory regions. 19 - clocks: Must contain references to controller clocks. 21 - clock-names: Must contain "mpmcclk" and "apb_pclk". 23 - clock-ranges: Empty property indicating that child nodes can inherit [all …]
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H A D | ti,gpmc-child.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Tony Lindgren <tony@atomide.com> 11 - Roger Quadros <rogerq@kernel.org> 24 gpmc,sync-clk-ps: 28 # Chip-select signal timings corresponding to GPMC_CONFIG2: 29 gpmc,cs-on-ns: 33 gpmc,cs-rd-off-ns: [all …]
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/openbmc/linux/arch/sh/include/mach-common/mach/ |
H A D | sh2007.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 25 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */ 28 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ 31 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ 34 /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ 37 /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ 40 /* burst count (0-3:4,8,16,32) */ 46 /* RD hold for SRAM (0-1:0,1) */ 49 /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */ 52 /* Multiplex (0-1:0,1) */ [all …]
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/openbmc/u-boot/drivers/net/phy/ |
H A D | miiphybb.c | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com> 11 * This provides a bit-banged interface to the ethernet MII management 100 .delay = bb_delay_wrap, 115 BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off); in bb_miiphy_init() 116 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off); in bb_miiphy_init() 117 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off); in bb_miiphy_init() 118 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off); in bb_miiphy_init() 119 BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off); in bb_miiphy_init() 120 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off); in bb_miiphy_init() [all …]
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/openbmc/linux/arch/powerpc/platforms/pasemi/ |
H A D | gpio_mdio.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2006-2007 PA Semi, Inc 9 * Based on drivers/net/fs_enet/mii-bitbang.c. 25 #define DELAY 1 macro 34 #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin) 35 #define MDIO_PIN(bus) (((struct gpio_priv *)bus->priv)->mdio_pin) 78 udelay(DELAY); in clock_out() 80 udelay(DELAY); in clock_out() 84 /* Utility to send the preamble, address, and register (common to read and write). */ 85 static void bitbang_pre(struct mii_bus *bus, int read, u8 addr, u8 reg) in bitbang_pre() argument [all …]
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/openbmc/linux/drivers/iio/common/ms_sensors/ |
H A D | ms_sensors_i2c.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (c) 2015 Measurement-Specialties 11 #include <linux/delay.h> 38 * ms_sensors_reset() - Reset function 41 * @delay: usleep minimal delay after reset command is issued 47 int ms_sensors_reset(void *cli, u8 cmd, unsigned int delay) in ms_sensors_reset() argument 54 dev_err(&client->dev, "Failed to reset device\n"); in ms_sensors_reset() 57 usleep_range(delay, delay + 1000); in ms_sensors_reset() 64 * ms_sensors_read_prom_word() - PROM word read function 66 * @cmd: PROM read cmd. Depends on device and prom id [all …]
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/openbmc/linux/Documentation/devicetree/bindings/mmc/ |
H A D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd) 7 and the properties used by the sdhci-sprd driver. 10 - compatible: Should contain "sprd,sdhci-r11". 11 - reg: physical base address of the controller and length. 12 - interrupts: Interrupts used by the SDHCI controller. 13 - clocks: Should contain phandle for the clock feeding the SDHCI controller 14 - clock-names: Should contain the following: 15 "sdio" - SDIO source clock (required) 16 "enable" - gate clock which used for enabling/disabling the device (required) 17 "2x_enable" - gate clock controlling the device for some special platforms (optional) [all …]
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/openbmc/linux/Documentation/i2c/ |
H A D | slave-testunit-backend.rst | 1 .. SPDX-License-Identifier: GPL-2.0 7 by Wolfram Sang <wsa@sang-engineering.com> in 2020 11 easy to obtain). Examples include multi-master testing, and SMBus Host Notify 21 # echo "slave-testunit 0x1030" > /sys/bus/i2c/devices/i2c-0/new_device 23 After that, you will have a write-only device listening. Reads will just return 24 an 8-bit version number of the testunit. When writing, the device consists of 4 25 8-bit registers and, except for some "partial" commands, all registers must be 29 0x00 CMD - which test to trigger 30 0x01 DATAL - configuration byte 1 for the test 31 0x02 DATAH - configuration byte 2 for the test [all …]
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/openbmc/u-boot/drivers/ddr/altera/ |
H A D | sequencer.c | 1 // SPDX-License-Identifier: BSD-3-Clause 3 * Copyright Altera Corporation (C) 2012-2015 44 * However, to support simulation-time selection of fast simulation mode, where 47 * check, which is based on the rtl-supplied value, or we dynamically compute 48 * the value to use based on the dynamically-chosen calibration mode 64 * non-skip and skip values 66 * The mask is set to include all bits when not-skipping, but is 70 static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */ 85 if (gbl->error_stage == CAL_STAGE_NIL) { in set_failing_group_stage() 86 gbl->error_substage = substage; in set_failing_group_stage() [all …]
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/openbmc/phosphor-hwmon/ |
H A D | hwmonio.hpp | 10 static constexpr auto delay = std::chrono::milliseconds{100}; 21 virtual int64_t read(const std::string& path) const = 0; 28 int64_t read(const std::string& path) const override; 38 * however, could in theory support non-sysfs handling of hwmon IO. 45 virtual int64_t read(const std::string& type, const std::string& id, 47 std::chrono::milliseconds delay) const = 0; 52 std::chrono::milliseconds delay) const = 0; 78 * @param[in] path - hwmon instance root - eg: 84 /** @brief Perform formatted hwmon sysfs read. 94 * @param[in] type - The hwmon type (ex. temp). [all …]
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/openbmc/phosphor-power/tools/power-utils/ |
H A D | aei_updater.cpp | 8 * http://www.apache.org/licenses/LICENSE-2.0 27 #include <phosphor-logging/lg2.hpp> 37 constexpr int ISP_STATUS_DELAY = 1200; // Delay for ISP status check (1.2s) 38 constexpr int MEM_WRITE_DELAY = 5000; // Memory write delay (5s) 39 constexpr int MEM_STRETCH_DELAY = 1; // Delay between writes (1ms) 40 constexpr int MEM_COMPLETE_DELAY = 2000; // Delay before completion (2s) 41 constexpr int REBOOT_DELAY = 8000; // Delay for reboot (8s) 43 constexpr uint8_t I2C_SMBUS_BLOCK_MAX = 0x20; // Max Read bytes from PSU 44 constexpr uint8_t FW_READ_BLOCK_SIZE = 0x20; // Read bytes from FW file 48 constexpr uint8_t STATUS_CML_INDEX = 0x4; // Status CML read index [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/ |
H A D | lpddr2.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 3 * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. 46 #define MMDC_MPMUR0_VALUE 0x00000800 /* Force delay line initialisation */ 55 #define MMDC_MPRDDLCTL_MODULE0_VALUE 0x4D4B4F4B /* Read delay line offsets */ 56 #define MMDC_MPWRDLCTL_MODULE0_VALUE 0x38383737 /* Write delay line offsets */ 57 #define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */ 58 #define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */ 60 #define MMDC_MPRDDLCTL_MODULE1_VALUE 0x4D4B4F4B /* Read delay line offsets */ 61 #define MMDC_MPWRDLCTL_MODULE1_VALUE 0x38383737 /* Write delay line offsets */ 62 #define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */ [all …]
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/openbmc/linux/drivers/md/ |
H A D | dm-delay.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2005-2007 Red Hat GmbH 17 #include <linux/device-mapper.h> 19 #define DM_MSG_PREFIX "delay" 24 unsigned int delay; member 36 struct delay_class read; member 56 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer() 61 mutex_lock(&dc->timer_lock); in queue_timeout() 63 if (!timer_pending(&dc->delay_timer) || expires < dc->delay_timer.expires) in queue_timeout() 64 mod_timer(&dc->delay_timer, expires); in queue_timeout() [all …]
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/openbmc/google-ipmi-sys/ |
H A D | handler.hpp | 7 // http://www.apache.org/licenses/LICENSE-2.0 17 #include <ipmid/api-types.hpp> 51 * Return ethernet details (hard-coded). 70 * @param[in] id - the cpld id number. 77 * Set the PSU Reset delay. 79 * @param[in] delay - delay in seconds. 82 virtual void psuResetDelay(std::uint32_t delay) const = 0; 97 * @param[in] id - the entity id value 98 * @param[in] instance - the entity instance 122 * Populate the i2c-pcie mapping vector. [all …]
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
H A D | jedec,lpddr3-timings.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin 10 - Krzysztof Kozlowski <krzk@kernel.org> 14 const: jedec,lpddr3-timings 19 Maximum DDR clock frequency for the speed-bin, in Hz. 20 Property is deprecated, use max-freq. 23 max-freq: [all …]
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H A D | jedec,lpddr3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3 10 - Krzysztof Kozlowski <krzk@kernel.org> 13 - $ref: jedec,lpddr-props.yaml# 18 - items: 19 - enum: 20 - samsung,K3QF2F20DB [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
H A D | emc.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 19 u32 read_config; /* Configures the dyn memory read strategy */ 23 u32 t_srex; /* Self-refresh exit time */ 27 u32 t_rfc; /* Auto-refresh period */ 28 u32 t_xsr; /* Exit self-refresh to active command time */ 31 u32 t_cdlr; /* Last data in to read command time */ 43 u32 waitwen; /* Delay from chip select to write enable */ 44 u32 waitoen; /* Delay to output enable */ 45 u32 waitrd; /* Delay to a read access */ 46 u32 waitpage; /* Delay for async page mode read */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/spi/ |
H A D | cdns,qspi-nor-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Peripheral-specific properties for the Cadence QSPI controller. 10 See spi-peripheral-props.yaml for more info. 13 - Vaishnav Achath <vaishnav.a@ti.com> 16 # cdns,qspi-nor.yaml 17 cdns,read-delay: 20 Delay for read capture logic, in clock cycles. [all …]
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/openbmc/linux/drivers/net/wireless/ath/ath9k/ |
H A D | rng.c | 27 u32 v1, v2, rng_last = sc->rng_last; in ath9k_rng_data_read() 28 struct ath_hw *ah = sc->sc_ah; in ath9k_rng_data_read() 50 sc->rng_last = rng_last; in ath9k_rng_data_read() 57 u32 delay; in ath9k_rng_delay_get() local 60 delay = 10; in ath9k_rng_delay_get() 62 delay = 1000; in ath9k_rng_delay_get() 64 delay = 10000; in ath9k_rng_delay_get() 66 return delay; in ath9k_rng_delay_get() 91 bytes_read = -EIO; in ath9k_rng_read() 98 struct ath_hw *ah = sc->sc_ah; in ath9k_rng_start() [all …]
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/openbmc/linux/drivers/input/touchscreen/ |
H A D | wm9712.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * wm9712.c -- Codec driver for Wolfson WM9712 AC97 Codecs. 16 #include <linux/delay.h> 65 * Set adc sample delay. 71 * This delay can be set by setting delay = n, where n is the array 72 * position of the delay in the array delay_table below. 76 static int delay = 3; variable 77 module_param(delay, int, 0); 78 MODULE_PARM_DESC(delay, "Set adc sample delay."); 87 MODULE_PARM_DESC(five_wire, "Set to '1' to use 5-wire touchscreen."); [all …]
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/openbmc/linux/include/linux/reset/ |
H A D | reset-simple.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 9 * Maxime Ripard <maxime.ripard@free-electrons.com> 16 #include <linux/reset-controller.h> 20 * struct reset_simple_data - driver data for simple reset controllers 21 * @lock: spinlock to protect registers during read-modify-write cycles 27 * @status_active_low: if true, bits read back as cleared while the reset is 28 * asserted. Otherwise, bits read back as set while the 30 * @reset_us: Minimum delay in microseconds needed that needs to be 32 * device. If multiple consumers with different delay 34 * be the largest minimum delay. 0 means that such a delay is
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