/openbmc/qemu/hw/misc/ |
H A D | npcm7xx_pwm.c | 2 * Nuvoton NPCM7xx PWM Module 19 #include "hw/qdev-clock.h" 20 #include "hw/qdev-properties.h" 25 #include "qemu/error-report.h" 64 /* Offset of each PWM channel's prescaler in the PPR register. */ 66 /* Offset of each PWM channel's clock selector in the CSR register. */ 68 /* Offset of each PWM channel's control variable in the PCR register. */ 77 if (!p->running) { in npcm7xx_pwm_calculate_freq() 81 csr = NPCM7XX_CSR(p->module->csr, p->index); in npcm7xx_pwm_calculate_freq() 82 ppr = NPCM7XX_PPR(p->module->ppr, p->index); in npcm7xx_pwm_calculate_freq() [all …]
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/openbmc/u-boot/arch/arm/cpu/armv7/s5p-common/ |
H A D | pwm.c | 1 // SPDX-License-Identifier: GPL-2.0+ 10 #include <pwm.h> 12 #include <asm/arch/pwm.h> 17 const struct s5p_timer *pwm = in pwm_enable() local 21 tcon = readl(&pwm->tcon); in pwm_enable() 24 writel(tcon, &pwm->tcon); in pwm_enable() 31 const struct s5p_timer *pwm = in pwm_disable() local 35 tcon = readl(&pwm->tcon); in pwm_disable() 38 writel(tcon, &pwm->tcon); in pwm_disable() 60 const struct s5p_timer *pwm = in pwm_config() local [all …]
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/openbmc/linux/drivers/pwm/ |
H A D | pwm-stmpe.c | 1 // SPDX-License-Identifier: GPL-2.0-only 15 #include <linux/pwm.h> 39 static int stmpe_24xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in stmpe_24xx_pwm_enable() argument 45 ret = stmpe_reg_read(stmpe_pwm->stmpe, STMPE24XX_PWMCS); in stmpe_24xx_pwm_enable() 47 dev_err(chip->dev, "error reading PWM#%u control\n", in stmpe_24xx_pwm_enable() 48 pwm->hwpwm); in stmpe_24xx_pwm_enable() 52 value = ret | BIT(pwm->hwpwm); in stmpe_24xx_pwm_enable() 54 ret = stmpe_reg_write(stmpe_pwm->stmpe, STMPE24XX_PWMCS, value); in stmpe_24xx_pwm_enable() 56 dev_err(chip->dev, "error writing PWM#%u control\n", in stmpe_24xx_pwm_enable() 57 pwm->hwpwm); in stmpe_24xx_pwm_enable() [all …]
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H A D | pwm-pxa.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * drivers/pwm/pwm-pxa.c 5 * simple driver for PWM (Pulse Width Modulator) controller 7 * 2008-02-13 initial version 10 * Links to reference manuals for some of the supported PWM chips can be found 14 * - When PWM is stopped, the current PWM period stops abruptly at the next 26 #include <linux/pwm.h> 34 /* PWM has_secondary_pwm? */ 35 { "pxa25x-pwm", 0 }, 36 { "pxa27x-pwm", HAS_SECONDARY_PWM }, [all …]
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H A D | pwm-lp3943.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * TI/National Semiconductor LP3943 PWM driver 15 #include <linux/pwm.h> 36 struct lp3943_platform_data *pdata = lp3943_pwm->pdata; in lp3943_pwm_request_map() 37 struct lp3943 *lp3943 = lp3943_pwm->lp3943; in lp3943_pwm_request_map() 39 int i, offset; in lp3943_pwm_request_map() local 43 return ERR_PTR(-ENOMEM); in lp3943_pwm_request_map() 45 pwm_map->output = pdata->pwms[hwpwm]->output; in lp3943_pwm_request_map() 46 pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs; in lp3943_pwm_request_map() 48 for (i = 0; i < pwm_map->num_outputs; i++) { in lp3943_pwm_request_map() [all …]
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H A D | pwm-atmel.c | 1 // SPDX-License-Identifier: GPL-2.0-only 8 * Links to reference manuals for the supported PWM chips can be found in 12 * - Periods start with the inactive level. 13 * - Hardware has to be stopped in general to update settings. 16 * - When atmel_pwm_apply() is called with state->enabled=false a change in 17 * state->polarity isn't honored. 18 * - Instead of sleeping to wait for a completed period, the interrupt 29 #include <linux/pwm.h> 32 /* The following is global registers for PWM controller */ 40 /* The following register is PWM channel related registers */ [all …]
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H A D | pwm-pca9685.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Driver for PCA9685 16-channel 12-bit PWM LED controller 8 * based on the pwm-twl-led.c driver 18 #include <linux/pwm.h> 28 * PWM channels requested afterwards must use a period that results in the same 97 /* No PWM enabled: Change allowed */ in pca9685_prescaler_can_change() 98 if (bitmap_empty(pca->pwms_enabled, PCA9685_MAXCHAN + 1)) in pca9685_prescaler_can_change() 100 /* More than one PWM enabled: Change not allowed */ in pca9685_prescaler_can_change() 101 if (bitmap_weight(pca->pwms_enabled, PCA9685_MAXCHAN + 1) > 1) in pca9685_prescaler_can_change() 104 * Only one PWM enabled: Change allowed if the PWM about to in pca9685_prescaler_can_change() [all …]
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H A D | pwm-spear.c | 21 #include <linux/pwm.h> 27 /* PWM registers and bits definitions */ 47 * struct spear_pwm_chip - struct representing pwm chip 49 * @mmio_base: base address of pwm chip 50 * @clk: pointer to clk structure of pwm chip 51 * @chip: linux pwm chip representation 65 unsigned long offset) in spear_pwm_readl() argument 67 return readl_relaxed(chip->mmio_base + (num << 4) + offset); in spear_pwm_readl() 71 unsigned int num, unsigned long offset, in spear_pwm_writel() argument 74 writel_relaxed(val, chip->mmio_base + (num << 4) + offset); in spear_pwm_writel() [all …]
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H A D | pwm-rcar.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * R-Car PWM Timer driver 8 * - The hardware cannot generate a 0% duty cycle. 20 #include <linux/pwm.h> 52 unsigned int offset) in rcar_pwm_write() argument 54 writel(data, rp->base + offset); in rcar_pwm_write() 57 static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset) in rcar_pwm_read() argument 59 return readl(rp->base + offset); in rcar_pwm_read() 63 unsigned int offset) in rcar_pwm_update() argument 67 value = rcar_pwm_read(rp, offset); in rcar_pwm_update() [all …]
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H A D | pwm-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Broadcom BCM7038 PWM driver 19 #include <linux/pwm.h> 41 * Maximum control word value allowed when variable-frequency PWM is used as a 42 * clock for the constant-frequency PMW. 61 unsigned int offset) in brcmstb_pwm_readl() argument 64 return __raw_readl(p->base + offset); in brcmstb_pwm_readl() 66 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl() 70 unsigned int offset) in brcmstb_pwm_writel() argument 73 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel() [all …]
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H A D | pwm-keembay.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Intel Keem Bay PWM driver 10 * - Upon disabling a channel, the currently running 22 #include <linux/pwm.h> 34 /* PWM Register offset */ 72 u32 val, u32 offset) in keembay_pwm_update_bits() argument 74 u32 buff = readl(priv->base + offset); in keembay_pwm_update_bits() 77 writel(buff, priv->base + offset); in keembay_pwm_update_bits() 92 static int keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in keembay_pwm_get_state() argument 100 clk_rate = clk_get_rate(priv->clk); in keembay_pwm_get_state() [all …]
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H A D | pwm-tiehrpwm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * EHRPWM PWM driver 5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/ 10 #include <linux/pwm.h> 122 static inline u16 ehrpwm_read(void __iomem *base, unsigned int offset) in ehrpwm_read() argument 124 return readw(base + offset); in ehrpwm_read() 127 static inline void ehrpwm_write(void __iomem *base, unsigned int offset, in ehrpwm_write() argument 130 writew(value, base + offset); in ehrpwm_write() 133 static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask, in ehrpwm_modify() argument 138 val = readw(base + offset); in ehrpwm_modify() [all …]
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H A D | pwm-sprd.c | 1 // SPDX-License-Identifier: GPL-2.0 13 #include <linux/pwm.h> 44 * The list of clocks required by PWM channels, and each channel has 2 clocks: 45 * enable clock and pwm clock. 56 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); in sprd_pwm_read() local 58 return readl_relaxed(spc->base + offset); in sprd_pwm_read() 64 u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); in sprd_pwm_write() local 66 writel_relaxed(val, spc->base + offset); in sprd_pwm_write() 69 static int sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in sprd_pwm_get_state() argument 74 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_get_state() [all …]
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H A D | pwm-berlin.c | 2 * Marvell Berlin PWM driver 6 * Author: Antoine Tenart <antoine.tenart@free-electrons.com> 19 #include <linux/pwm.h> 61 unsigned int channel, unsigned long offset) in berlin_pwm_readl() argument 63 return readl_relaxed(bpc->base + channel * 0x10 + offset); in berlin_pwm_readl() 68 unsigned long offset) in berlin_pwm_writel() argument 70 writel_relaxed(value, bpc->base + channel * 0x10 + offset); in berlin_pwm_writel() 73 static int berlin_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in berlin_pwm_request() argument 79 return -ENOMEM; in berlin_pwm_request() 81 return pwm_set_chip_data(pwm, channel); in berlin_pwm_request() [all …]
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H A D | pwm-dwc.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * DesignWare PWM Controller driver 5 * Copyright (C) 2018-2020 Intel Corporation 12 * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low 22 #include <linux/pwm.h> 60 static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) in dwc_pwm_readl() argument 62 return readl(dwc->base + offset); in dwc_pwm_readl() 65 static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset) in dwc_pwm_writel() argument 67 writel(value, dwc->base + offset); in dwc_pwm_writel() 70 static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) in __dwc_pwm_set_enable() argument [all …]
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H A D | pwm-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * drivers/pwm/pwm-tegra.c 5 * Tegra pulse-width-modulation controller driver 7 * Copyright (c) 2010-2020, NVIDIA Corporation. 8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de> 11 * 1. 13-bit: Frequency division (SCALE) 12 * 2. 8-bit : Pulse division (DUTY) 13 * 3. 1-bit : Enable bit 15 * The PWM clock frequency is divided by 256 before subdividing it based 17 * frequency for PWM output. The maximum output frequency that can be [all …]
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H A D | pwm-sun4i.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> 8 * - When outputing the source clock directly, the PWM logic will be bypassed 21 #include <linux/pwm.h> 47 #define PWM_PRD(prd) (((prd) - 1) << 16) 99 unsigned long offset) in sun4i_pwm_readl() argument 101 return readl(chip->base + offset); in sun4i_pwm_readl() 105 u32 val, unsigned long offset) in sun4i_pwm_writel() argument 107 writel(val, chip->base + offset); in sun4i_pwm_writel() 111 struct pwm_device *pwm, in sun4i_pwm_get_state() argument [all …]
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/openbmc/qemu/tests/qtest/ |
H A D | npcm7xx_pwm-test.c | 2 * QTests for Nuvoton NPCM7xx PWM Modules. 58 /* MFT (PWM fan) related */ 106 typedef struct PWM { struct 111 } PWM; argument 115 const PWM *pwm; member 129 static const PWM pwm_list[] = { 201 /* Returns the index of the PWM module. */ 204 ptrdiff_t diff = module - pwm_module_list; in pwm_module_index() 211 /* Returns the index of the PWM entry. */ 212 static int pwm_index(const PWM *pwm) in pwm_index() argument [all …]
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/openbmc/linux/Documentation/devicetree/bindings/gpio/ |
H A D | gpio-mvebu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 11 - Andrew Lunn <andrew@lunn.ch> 16 - enum: 17 - marvell,armada-8k-gpio 18 - marvell,orion-gpio 20 - items: [all …]
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/openbmc/linux/drivers/leds/ |
H A D | leds-pca9532.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * pca9532.c - 16-bit Led dimmer 18 #include <linux/leds-pca9532.h> 48 u8 pwm[2]; member 101 .name = "leds-pca953x", 109 /* We have two pwm/blinkers, but 16 possible leds to drive. Additionally, 110 * the clever Thecus people are using one pwm to drive the beeper. So, 111 * as a compromise we average one pwm to the values requested by all 114 static int pca9532_calcpwm(struct i2c_client *client, int pwm, int blink, in pca9532_calcpwm() argument 119 for (i = 0; i < data->chip_info->num_leds; i++) { in pca9532_calcpwm() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/reset/ |
H A D | intel,rcu-gw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dilip Kota <eswara.kota@linux.intel.com> 15 - intel,rcu-lgm 16 - intel,rcu-xrx200 22 intel,global-reset: 23 description: Global reset register offset and bit offset. 24 $ref: /schemas/types.yaml#/definitions/uint32-array [all …]
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/openbmc/linux/Documentation/hwmon/ |
H A D | lm85.rst | 79 - Philip Pokorny <ppokorny@penguincomputing.com>, 80 - Frodo Looijaard <frodol@dds.nl>, 81 - Richard Barrington <rich_b_nz@clear.net.nz>, 82 - Margit Schubert-While <margitsw@t-online.de>, 83 - Justin Thiessen <jthiessen@penguincomputing.com> 86 ----------- 92 The LM85 uses the 2-wire interface compatible with the SMBUS 2.0 94 temperatures and five (5) voltages. It has four (4) 16-bit counters for 96 VID signals from the processor to the VRM. Lastly, there are three (3) PWM 110 A sophisticated control system for the PWM outputs is designed into the [all …]
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/openbmc/qemu/hw/timer/ |
H A D | exynos4210_pwm.c | 4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. 39 do { fprintf(stdout, "PWM: [%24s:%5d] " fmt, __func__, __LINE__, \ 105 #define TYPE_EXYNOS4210_PWM "exynos4210.pwm" 123 .name = "exynos4210.pwm.pwm", 137 .name = "exynos4210.pwm", 152 * PWM update frequency. 154 * for s->timer[id].ptimer. 159 freq = s->timer[id].freq; in exynos4210_pwm_update_freq() 161 s->timer[id].freq = 24000000 / in exynos4210_pwm_update_freq() 162 ((GET_PRESCALER(s->reg_tcfg[0], 1) + 1) * in exynos4210_pwm_update_freq() [all …]
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/openbmc/u-boot/arch/sandbox/include/asm/ |
H A D | test.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 3 * Test-related constants for sandbox 42 * sandbox_i2c_set_test_mode() - set test mode for running unit tests 66 * offset: number of milliseconds to advance the system time 68 void sandbox_timer_add_offset(unsigned long offset); 71 * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time 75 * @offset: RTC offset from current system/base time (-1 for no 77 * @return old value of RTC offset 80 int offset); 83 * sandbox_i2c_rtc_get_set_base_time() - get and set the base time [all …]
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/openbmc/linux/drivers/gpio/ |
H A D | gpio-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 19 * - the basic variant, called "orion-gpio", with the simplest 21 * non-SMP Discovery systems 22 * - the mv78200 variant for MV78200 Discovery systems. This variant 26 * - the armadaxp variant for Armada XP systems. This variant keeps 28 * interrupts are used, but adds per-CPU cause/edge mask/level mask 29 * registers n a separate memory area for the per-CPU GPIO 48 #include <linux/pwm.h> [all …]
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