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/openbmc/u-boot/doc/device-tree-bindings/pwm/
H A Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
[all …]
H A Dtegra20-pwm.txt4 - compatible: should be one of:
5 - "nvidia,tegra20-pwm"
6 - "nvidia,tegra30-pwm"
7 - reg: physical base address and length of the controller's registers
8 - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
9 first cell specifies the per-chip index of the PWM to use and the second
14 pwm: pwm@7000a000 {
15 compatible = "nvidia,tegra20-pwm";
17 #pwm-cells = <2>;
/openbmc/openbmc-tools/pwmtachtool/src/
H A Dpwmtachtool.c4 * This application provides functions to get/set fan speed / PWM dutycycle.
44 printf ("Copyright (c) 2009-2015 American Megatrends Inc.\n"); in ShowUsage()
45 printf( "Usage : pwmtachtool <device_id> <command-option> <fannum>\n" ); in ShowUsage()
46 printf( "\t--set-fan-speed: Set Fan's speed. Takes the RPM value as the last argument\n" ); in ShowUsage()
48 …printf( "\t--set-pwm-dutycycle: Set Fan's dutycycle. dutycycle_percentage value should be … in ShowUsage()
49 …printf( "\t--set-pwm-dutycycle-value: Set Fan's dutycycle. dutycycle_value should be between 0 t… in ShowUsage()
51 printf( "\t--get-pwm-dutycycle: Get Fan's dutycycle\n"); in ShowUsage()
52 printf( "\t--get-fan-speed: Get Fan's speed\n" ); in ShowUsage()
53 printf( "\t--verbose: Enable Debug messages\n" ); in ShowUsage()
71 return -1; in process_arguments()
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H A Dpwmtach.c36 //build the pwm and tach access device node file name, and mapping pwm/tach number starting from 1.
37 …NUM) snprintf(buffer, sizeof(buffer), "%s%d%s%d", HWMON_DIR "/hwmon",DEV_ID, "/pwm", PWM_NUM+1)
54 retval = -1; in pwmtach_directory_check()
58 //Notice: dutycycle_value is one byte (0-255)
72 dutycycle_value = ppwmtach_arg->dutycycle; in SET_PWM_DUTYCYCLE_VALUE()
73 BUILD_PWM_NODE_NAME(DevNodeFileName,ppwmtach_arg->dev_id,ppwmtach_arg->pwmnumber); in SET_PWM_DUTYCYCLE_VALUE()
88 …printf("%s: Error write dutycycle value %d to pwm %d\n",__FUNCTION__,dutycycle_value,ppwmtach_arg-… in SET_PWM_DUTYCYCLE_VALUE()
89 retval = -1; in SET_PWM_DUTYCYCLE_VALUE()
102 if(ppwmtach_arg->dutycycle > 100) in SET_PWM_DUTYCYCLE()
104 return -1; in SET_PWM_DUTYCYCLE()
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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dtegra20-dc.txt2 ------------------
5 U-Boot, and may change based on Linux activity)
12 - compatible : Should be "nvidia,tegra20-dc"
17 - nvidia,panel : phandle of LCD panel information
24 - nvidia,bits-per-pixel: number of bits per pixel (depth)
25 - nvidia,pwm : pwm to use to set display contrast (see tegra20-pwm.txt)
26 - nvidia,panel-timings: 4 cells containing required timings in ms:
28 * delay between panel_vdd-rise and data-rise
29 * delay between data-rise and backlight_vdd-rise
30 * delay between backlight_vdd and pwm-rise
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H A Dexynos-fb.txt5 compatible: should be "samsung,exynos-fimd"
9 samsung,vl-col: X resolution of the panel
10 samsung,vl-row: Y resolution of the panel
11 samsung,vl-freq: Refresh rate
12 samsung,vl-bpix: Bits per pixel
13 samsung,vl-hspw: Hsync value
14 samsung,vl-hfpd: Right margin
15 samsung,vl-hbpd: Left margin
16 samsung,vl-vspw: Vsync value
17 samsung,vl-vfpd: Lower margin
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/openbmc/u-boot/arch/sandbox/include/asm/
H A Dtest.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Test-related constants for sandbox
42 * sandbox_i2c_set_test_mode() - set test mode for running unit tests
66 * offset: number of milliseconds to advance the system time
71 * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time
75 * @offset: RTC offset from current system/base time (-1 for no
83 * sandbox_i2c_rtc_get_set_base_time() - get and set the base time
86 * @base_time: New base system time (set to -1 for no change)
94 * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD
103 * sandbox_pwm_get_config() - get the PWM config for a channel
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/openbmc/qemu/include/hw/misc/
H A Dnpcm7xx_pwm.h2 * Nuvoton NPCM7xx PWM Module
23 /* Each PWM module holds 4 PWM channels. */
27 * Number of registers in one pwm module. Don't change this without increasing
34 * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
35 * value of 100,000 the duty cycle for that PWM is 10%.
42 * struct NPCM7xxPWM - The state of a single PWM channel.
43 * @module: The PWM module that contains this channel.
45 * @running: Whether this PWM channel is generating output.
46 * @inverted: Whether this PWM channel is inverted.
47 * @index: The index of this PWM channel.
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/openbmc/entity-manager/schemas/
H A Dintel.json2 "$schema": "http://json-schema.org/draft-07/schema#",
16 "Pwm": { object
17 "type": "number"
24 "type": "number"
32 "required": ["Name", "Type", "Status", "Pwm", "Tachs"],
/openbmc/bmcweb/redfish-core/schema/oem/openbmc/json-schema/
H A DOpenBMCManager.v1_0_0.json2 …"$id": "https://github.com/openbmc/bmcweb/tree/master/redfish-core/schema/oem/openbmc/json-schema/…
3 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
11 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
17 "number",
87 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
93 "number",
105 "type": "number"
111 "type": "number"
117 "type": "number"
123 "type": "number"
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/openbmc/qemu/include/hw/timer/
H A Dsifive_pwm.h2 * SiFive PWM
34 #define TYPE_SIFIVE_PWM "sifive-pwm"
50 * if en bit(s) set, is the number of ticks when pwmcount was 0
51 * if en bit(s) not set, is the number of ticks in pwmcount
/openbmc/u-boot/doc/device-tree-bindings/video/bridge/
H A Dps8622.txt1 ps8622-bridge bindings
4 - compatible: "parade,ps8622" or "parade,ps8625"
5 - reg: first i2c address of the bridge
6 - sleep-gpios: OF device-tree gpio specification for PD_ pin.
7 - reset-gpios: OF device-tree gpio specification for RST_ pin.
8 - parade,regs: List of 3-byte registers tuples to write:
12 - lane-count: number of DP lanes to use
13 - use-external-pwm: backlight will be controlled by an external PWM
14 - video interfaces: Device node can contain video interface port
17 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
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/openbmc/u-boot/drivers/video/
H A Dpwm_backlight.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <pwm.h>
17 * Private information for the PWM backlight
21 * Otherwise the levels are an index into @levels (0..n-1).
25 * @pwm: PWM to use to change the backlight brightness
26 * @channel: PWM channel to use
29 * @num_levels: Number of levels
39 struct udevice *pwm; member
56 duty_cycle = priv->period_ns * (priv->cur_level - priv->min_level) / in set_pwm()
57 (priv->max_level - priv->min_level + 1); in set_pwm()
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/openbmc/u-boot/arch/arm/cpu/armv7/s5p-common/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/pwm.h>
15 /* Use the old PWM interface for now */
17 #include <pwm.h>
42 return readl(&timer->tcnto4); in timer_get_us_down()
47 /* PWM Timer 4 */ in timer_init()
53 gd->arch.timer_reset_value = 0; in timer_init()
56 gd->arch.lastinc = timer_get_us_down(); in timer_init()
76 gd->arch.timer_reset_value += gd->arch.lastinc - now; in get_timer()
77 gd->arch.lastinc = now; in get_timer()
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/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dmarvell,armada-37xx-pinctrl.txt7 ------------------------
11 Refer to pinctrl-bindings.txt in this directory for details of the
17 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
19 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
21 - reg: The first set of registers is for pinctrl/GPIO and the second
23 - interrupts: list of interrupts used by the GPIO
28 - pins 20-24
29 - functions jtag, gpio
32 - pins 8-10
33 - functions sdio, gpio
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/openbmc/u-boot/include/
H A Dtps6586x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 /* SM0-2 PWM/PFM Mode Selection */
18 * Enable PWM mode for selected SM0-2
21 * @return 0 if ok, -1 on error
35 * done and an error will be reported. Use -1 to skip
37 * @return 0 if ok, -1 on error
43 * Set up the TPS6586X I2C bus number. This will be used for all operations
/openbmc/dbus-sensors/src/fan/
H A DFanMain.cpp8 // http://www.apache.org/licenses/LICENSE-2.0
31 #include <phosphor-logging/lg2.hpp>
70 "sensorTypes element number is not equal to FanTypes number");
80 {"aspeed,ast2400-pwm-tacho", FanTypes::aspeed},
81 {"aspeed,ast2500-pwm-tach
176 findPwmPath(const std::filesystem::path & directory,unsigned int pwm,std::filesystem::path & pwmPath) findPwmPath() argument
560 size_t pwm = std::visit(VariantToUnsignedIntVisitor(), createSensors() local
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/openbmc/qemu/include/hw/arm/
H A Dnpcm8xx.h20 #include "hw/core/split-irq.h"
37 #include "hw/usb/hcd-ehci.h"
38 #include "hw/usb/hcd-ohci.h"
60 * PWM fan splitter. each splitter connects to one PWM output and
93 NPCM7xxPWMState pwm[NPCM8XX_NR_PWM_MODULES]; member
114 /* Number of CPU cores enabled in this SoC class. */
122 * npcm8xx_load_kernel - Loads memory with everything needed to boot
123 * @machine - The machine containing the SoC to be booted.
124 * @soc - The SoC containing the CPU to be booted.
H A Dnpcm7xx.h21 #include "hw/core/split-irq.h"
37 #include "hw/usb/hcd-ehci.h"
38 #include "hw/usb/hcd-ohci.h"
60 * PWM fan splitter. each splitter connects to one PWM output and
96 NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES]; member
124 /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */
129 * npcm7xx_load_kernel - Loads memory with everything needed to boot
130 * @machine - The machine containing the SoC to be booted.
131 * @soc - The SoC containing the CPU to be booted.
/openbmc/u-boot/board/rockchip/evb_rk3399/
H A Devb-rk3399.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <dm/uclass-internal.h>
20 * The PWM do not have decicated interrupt number in dts and can in board_init()
22 * The PWM2 and PWM3 are for pwm regulater. in board_init()
61 debug("%s vcc5v0-host-en set fail!\n", __func__); in board_init()
/openbmc/openbmc/meta-facebook/meta-ventura/recipes-ventura/plat-svc/files/
H A Dventura-early-sys-init2 # shellcheck source=meta-facebook/recipes-fb/obmc_functions/files/fb-common-functions
3 source /usr/libexec/fb-common-functions
5 # 88E6393X PWRGD gpio number
19 output=$(i2ctransfer -y 14 w4@0x40 0xE0 0x00 0x00 0x00 r4 2>/dev/null)
22 response=$(echo "$output" | grep -oE '0x[0-9a-fA-F]{2}' | sed 's/0x//' | tr 'A-F' 'a-f' | xargs)
24 log-create xyz.openbmc_project.State.SMC.SMCFailed --json \
30 #Set fixed PWM to 80% before power brick.
34 mainsource=$(i2cget -y -f 18 0x20)
36 if [[ -n "$mainsource" && "$mainsource" =~ ^0[xX][0-9a-fA-F]+$ ]]; then
37 #Set fixed max31790 PWM to 80%
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/openbmc/qemu/docs/system/arm/
H A Draspi.rst8 ARM1176JZF-S core, 512 MiB of RAM
10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
19 -------------------
21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU
27 * Serial ports (BCM2835 AUX - 16550 based - and PL011)
28 * Random Number Generator (RNG)
41 ---------------
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/openbmc/qemu/hw/arm/
H A Dnpcm8xx.c23 #include "hw/char/serial-mm.h"
27 #include "hw/qdev-clock.h"
28 #include "hw/qdev-properties.h"
84 * Interrupt lines going into the GIC. This does not include internal Cortex-A35
119 NPCM8XX_PWM0_IRQ = 93, /* PWM module 0 */
120 NPCM8XX_PWM1_IRQ, /* PWM module 1 */
175 /* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */
178 ((NPCM8XX_NUM_IRQ - GIC_INTERNAL) + (cpu) * GIC_INTERNAL)
198 /* Direct memory-mapped access to SPI0 CS0-1. */
204 /* Direct memory-mapped access to SPI1 CS0-3. */
[all …]
H A Dnpcm7xx.c21 #include "hw/char/serial-mm.h"
24 #include "hw/qdev-clock.h"
25 #include "hw/qdev-properties.h"
30 #include "target/arm/cpu-qom.h"
79 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
131 NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
132 NPCM7XX_PWM1_IRQ, /* PWM module 1 */
153 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
171 /* Direct memory-mapped access to SPI0 CS0-1. */
177 /* Direct memory-mapped access to SPI3 CS0-3. */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos5420-peach-pit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG/GOOGLE Peach-Pit board device tree source
9 /dts-v1/;
11 #include <dt-bindings/clock/maxim,max77802.h>
12 #include <dt-bindings/regulator/maxim,max77802.h>
17 compatible = "google,pit-rev#", "google,pit",
21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
22 hwid = "PIT TEST A-A 7848";
23 lazy-init = <1>;
34 compatible = "pwm-backlight";
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