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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atombios.c569 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; in amdgpu_atombios_get_clock_info() local
576 ppll->reference_freq = in amdgpu_atombios_get_clock_info()
578 ppll->reference_div = 0; in amdgpu_atombios_get_clock_info()
580 ppll->pll_out_min = in amdgpu_atombios_get_clock_info()
582 ppll->pll_out_max = in amdgpu_atombios_get_clock_info()
585 ppll->lcd_pll_out_min = in amdgpu_atombios_get_clock_info()
587 if (ppll->lcd_pll_out_min == 0) in amdgpu_atombios_get_clock_info()
588 ppll->lcd_pll_out_min = ppll->pll_out_min; in amdgpu_atombios_get_clock_info()
589 ppll->lcd_pll_out_max = in amdgpu_atombios_get_clock_info()
591 if (ppll->lcd_pll_out_max == 0) in amdgpu_atombios_get_clock_info()
[all …]
H A Damdgpu_pll.c288 * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
292 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
293 * also in DP mode. For DP, a single PPLL can be used for all DP
317 * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
321 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
H A Ddce_v8_0.c2112 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2116 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2117 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2118 * monitors a dedicated PPLL must be used. If a particular board has
2143 /* skip PPLL programming if using ext clock */ in dce_v8_0_pick_pll()
2146 /* use the same PPLL for all DP monitors */ in dce_v8_0_pick_pll()
2152 /* use the same PPLL for all monitors with the same clock */ in dce_v8_0_pick_pll()
2166 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2177 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v8_0_pick_pll()
2493 /* disable the ppll */ in dce_v8_0_crtc_disable()
[all …]
H A Ddce_v11_0.c2259 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2263 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2264 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2265 * monitors a dedicated PPLL must be used. If a particular board has
2323 /* skip PPLL programming if using ext clock */ in dce_v11_0_pick_pll()
2326 /* use the same PPLL for all DP monitors */ in dce_v11_0_pick_pll()
2332 /* use the same PPLL for all monitors with the same clock */ in dce_v11_0_pick_pll()
2345 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2354 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v11_0_pick_pll()
2673 /* disable the ppll */ in dce_v11_0_crtc_disable()
[all …]
H A Datombios_crtc.c836 pll = &adev->clock.ppll[0]; in amdgpu_atombios_crtc_set_pll()
839 pll = &adev->clock.ppll[1]; in amdgpu_atombios_crtc_set_pll()
844 pll = &adev->clock.ppll[2]; in amdgpu_atombios_crtc_set_pll()
H A Ddce_v10_0.c2218 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2222 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2223 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2224 * monitors a dedicated PPLL must be used. If a particular board has
2249 /* skip PPLL programming if using ext clock */ in dce_v10_0_pick_pll()
2252 /* use the same PPLL for all DP monitors */ in dce_v10_0_pick_pll()
2258 /* use the same PPLL for all monitors with the same clock */ in dce_v10_0_pick_pll()
2272 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v10_0_pick_pll()
2589 /* disable the ppll */ in dce_v10_0_crtc_disable()
2652 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v10_0_crtc_mode_fixup()
H A Ddce_v6_0.c2134 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2138 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2139 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2140 * monitors a dedicated PPLL must be used. If a particular board has
2158 /* skip PPLL programming if using ext clock */ in dce_v6_0_pick_pll()
2163 /* use the same PPLL for all monitors with the same clock */ in dce_v6_0_pick_pll()
2175 DRM_ERROR("unable to allocate a PPLL\n"); in dce_v6_0_pick_pll()
2489 /* disable the ppll */ in dce_v6_0_crtc_disable()
2553 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v6_0_crtc_mode_fixup()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Datombios_crtc.c1742 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1746 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1747 * also in DP mode. For DP, a single PPLL can be used for all DP
1776 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1780 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1826 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1830 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1831 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1832 * monitors a dedicated PPLL must be used. If a particular board has
1875 /* skip PPLL programming if using ext clock */ in radeon_atom_pick_pll()
[all …]
H A Datombios.h1545 // 0 means disable PPLL
1552 UCHAR ucCRTC; // Which CRTC uses this Ppll
1565 // 0 means disable PPLL
1572 UCHAR ucCRTC; // Which CRTC uses this Ppll
1612 … // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1625 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1641 // 0 means disable PPLL/DCPLL.
1649 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1652 // bit[4]= RefClock source for PPLL.
1675 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
[all …]
H A Dradeon_encoders.c54 /* DVO requires 2x ppll clocks depending on tmds chip */ in radeon_encoder_clones()
/openbmc/u-boot/drivers/video/
H A Dati_radeon_fb.c217 /* We still have to force a switch to selected PPLL div thanks to in radeon_write_pll_regs()
231 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ in radeon_write_pll_regs()
234 /* Reset PPLL & enable atomic update */ in radeon_write_pll_regs()
239 /* Switch to selected PPLL divider */ in radeon_write_pll_regs()
244 /* Set PPLL ref. div */ in radeon_write_pll_regs()
263 /* Set PPLL divider 3 & post divider*/ in radeon_write_pll_regs()
289 /* Switch back VCLK source to PPLL */ in radeon_write_pll_regs()
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx35.c60 static const char *std_sel[] = {"ppll", "arm"};
64 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
109 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3399.c23 ppll, enumerator
136 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
140 "ppll" };
145 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
150 "ppll", "upll", "xin24m" };
210 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
211 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
236 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
1407 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1428 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
[all …]
H A Dclk-rk3588.c41 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, enumerator
533 PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" };
534 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
692 [ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
2163 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0,
2166 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0,
2169 COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0,
2310 GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0,
2312 GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0,
2314 GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0,
[all …]
H A Dclk-rk3568.c19 ppll, hpll, enumerator
289 PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"};
307 PNAME(clk_pdpmu_p) = { "ppll", "gpll" };
308 PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
314 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
1462 FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2),
1463 FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2),
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dimx35-clock.yaml21 ppll 2
/openbmc/linux/drivers/gpu/drm/amd/display/include/
H A Dbios_parser_types.h208 * other ppll params */
211 * other ppll params */
/openbmc/linux/include/dt-bindings/clock/
H A Dxlnx-versal-clk.h19 #define PPLL 10 macro
/openbmc/linux/Documentation/gpu/amdgpu/display/
H A Ddc-glossary.rst41 * PPLL: Pixel PLL
/openbmc/linux/drivers/video/fbdev/aty/
H A Dradeon_base.c1365 /* We still have to force a switch to selected PPLL div thanks to in radeon_write_pll_regs()
1377 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ in radeon_write_pll_regs()
1380 /* Reset PPLL & enable atomic update */ in radeon_write_pll_regs()
1385 /* Switch to selected PPLL divider */ in radeon_write_pll_regs()
1392 /* Set PPLL ref. div */ in radeon_write_pll_regs()
1411 /* Set PPLL divider 3 & post divider*/ in radeon_write_pll_regs()
1437 /* Switch back VCLK source to PPLL */ in radeon_write_pll_regs()
1826 /* Calculate PPLL value if necessary */ in radeonfb_set_par()
H A Dradeon_pm.c1662 /* Restore our "reference" PPLL divider set by firmware in radeon_pm_restore_pixel_pll()
2088 /* PPLL and P2PLL default values & off */ in radeon_reinitialize_M9P()
2205 /* Restore PPLL, spread spectrum & LVDS */ in radeon_reinitialize_M9P()
H A Dradeon_monitor.c673 "from PPLL %d\n", in radeon_fixup_panel_info()
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Datombios.h1820 // 0 means disable PPLL
1827 UCHAR ucCRTC; // Which CRTC uses this Ppll
1840 // 0 means disable PPLL
1847 UCHAR ucCRTC; // Which CRTC uses this Ppll
1887 … // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1900 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1917 // 0 means disable PPLL/DCPLL.
1925 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1928 // bit[4]= RefClock source for PPLL.
1951 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
[all …]
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3399.c556 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ in rk3399_i2c_set_clk()
1371 /* configure pmu pll(ppll) */ in pmuclk_init()
H A Dclk_rv1108.c450 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ in rv1108_i2c_set_clk()

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